Fabrication of a T-shaped capacitor

Details Fabrication of a T-shaped capacitor Fabrication of a T-shaped capacitor

2001-03-22

2002-06-04

Christianson, Keith (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S308000, C257S310000

Reexamination Certificate

active

06399980

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a structure and a manufacturing method of a capacitor, and especially to a structure and a manufacturing method of a capacitor applied to the dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
It is well known that the capacity of a capacitor is related to the quality of dynamic random access memory (DRAM). Therefore, many methods have been developed for increasing the capacity of capacitor.
First of all, please refer to FIGS.
1
(
a
) and
1
(
b
) showing conventional method for manufacturing a capacitor. This method is described as follows.
Shown in FIG.
1
(
a
) includes the steps of (1) forming an interlayer dielectric (ILD)
11
over a silicon substrate
10
by chemical vapor deposition (CVD) or lower pressure chemical vapor deposition (LPCVD), (2) defining a contact window by photolithography and partially removing the ILD
11
to form the contact window
12
, (3) forming a doped polysilicon layer
13
with a thickness of 1000 Å over the ILD
11
and in the contact window
12
by LPCVD, and (4) forming a rugged polysilicon layer
14
with a thickness of 850 Å over the doped polysilicon layer
13
to increase the surface area of the capacitor.
In FIG.
1
(
b
), the steps include: 1) defining the capacitor region by photolithography and partially etching the rugged polysilicon layer
14
and the doped polysilicon layer
13
to expose a portion of the ILD
11
; 2) forming an oxide-on-nitride-on-oxide (ONO) layer
15
on the rugged polysilicon layer
14
and the ILD
11
and alongside the doped polysilicon layer
13
by LPCVD; and 3) forming another doped polysilicon layer
16
over the ONO layer
15
to construct the conventional capacitor.
Please refer to
FIG. 2
showing another conventional method. The detailed steps are illustrated as follows.
In FIG.
2
(
a
), the steps include: (1) forming an interlayer dielectric (ILD)
21
over a silicon substrate
20
by chemical vapor deposition (CVD), (2) forming a silicon nitride
22
on ILD
21
, wherein the silicon nitride
22
has a thickness of 100 Å~300 Å and serves as an etching stop layer, (3) forming a sacrificial oxide
23
on the silicon nitride
22
by CVD, (4) defining a contact window by photolithography and partially removing the ILD
21
, the silicon nitride
22
, and the sacrificial oxide
23
to form the contact window
24
, and (5) forming a doped polysilicon layer
25
with a thickness of 1000 Å over the sacrificial oxide
23
and in the contact window
24
by LPCVD.
In FIG.
2
(
b
), the steps include: 1) defining the capacitor region by photolithography and partially etching the doped polysilicon layer
25
; 2) etching the sacrificial oxide
23
by using a buffer over etching (B.O.E.) solution containing hydrofluoric acid (HF) to expose the silicon nitride
22
; 3) forming an oxide-on-nitride-on-oxide (ONO) layer
26
on the silicon nitride
22
and a top and sidewalls of the doped polysilicon layer
25
by LPCVD; and 4) forming another doped polysilicon layer
27
on the ONO layer
26
to construct the capacitor.
In addition, there is another method as shown in FIG.
3
. This method is described as follows.
In FIG.
3
(
a
), the steps include: (1) forming an interlayer dielectric (ILD)
31
over a silicon substrate
30
by CVD, (2) forming a silicon nitride
32
on ILD
31
, wherein the silicon nitride
32
has a thickness of 100 Å~300 Å and serves as an etching stop layer, (3) forming a first sacrificial oxide
33
on the silicon nitride
32
by CVD, (4) defining a contact window by photolithography and partially removing the first sacrificial oxide
33
, the silicon nitride
32
, and the ILD
31
to form the contact window
34
, (5) forming a first doped polysilicon layer
35
with a thickness of 1000 Å over the first sacrificial oxide
33
and in the contact window
34
by LPCVD, and (6) forming a second sacrificial oxide
36
on the first doped polysilicon layer
35
by CVD.
In FIG.
3
(
b
), the steps include: 1) defining the capacitor region by photolithography and partially etching the second sacrificial oxide
36
, the first doped polysilicon layer
35
, and the first sacrificial oxide
33
, wherein the silicon nitride
32
serves as an etching stop layer; 2) forming a second doped polysilicon layer
37
on the top surface of the second sacrificial oxide
36
, alongside the second sacrificial oxide
36
, the first doped polysilicon layer
35
, and the first sacrificial oxide
33
, as well as on the silicon nitride
32
.
In FIG.
3
(
c
), the second doped polysilicon layer
37
is etched by dry etching (i.e. an anisotropic etching) to expose the top surface of the second sacrificial oxide
36
and a portion of the silicon nitride
32
.
In FIG.
3
(
d
), the second sacrificial oxide
36
is completely removed by using a buffer over etching (B.O.E.) solution containing hydrofluoric acid (HF) to expose the first doped polysilicon layer
35
. Thereafter, an oxide-on-nitride-on-oxide (ONO) layer
38
is formed over the portion of the silicon nitride
32
, the second doped polysilicon layer
37
, and the first doped polysilicon layer
35
by LPCVD. Finally, another doped polysilicon layer
39
is formed on the ONO layer
38
to construct the capacitor.
However, these conventional methods have some defects described as follows:
1. In FIGS.
1
(
a
) and
1
(
b
), the rugged polysilicon layer in the fixed capacitor region cannot effectively increase the surface area of the capacitor. Therefore, the maximum capacity can be only increased up to two times by such a method using the rugged polysilicon layer to increase the surface area of the capacitor. Because the size of the capacitor will be getting smaller in the future, this method may be no longer effective then.
2. In the method of FIGS.
2
(
a
) and
2
(
b
), the sacrificial oxide is formed and then is etched to increase the surface area of the capacitor, but the effect is not good enough.
3. In the method as shown in FIGS.
3
(
a
)-
3
(
d
), the cylindrical doped polysilicon can increase the surface area of the capacitor which is constructed with a doped polysilicon layer, the ONO layer, and another doped polysilicon layer. However, it can be seen from FIG.
3
(
d
) that the surface of the capacitor is so irregular that it will seriously influence the subsequent planarization process of the semiconductor.
Therefore, the present invention is developed to improve the above-described disadvantages.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a manufacturing method which can effectively increase the density and intensity of the capacitor applied to the memory unit with high density.
Another object of the present invention is to provide a structure and a manufacturing method for promoting the yield rate of a capacitor.
According to the present invention, the method for manufacturing a capacitor, applied to a memory unit including a substrate having a dielectric layer formed thereon and an etching stop layer formed on said dielectric layer, includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer, wherein the portion of the first conducting layer and the portion of the second

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