Fabrication of a notched gate structure for a field effect...

Details Fabrication of a notched gate structure for a field effect... Fabrication of a notched gate structure for a field effect...

2000-07-10

2002-06-04

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S591000, C438S669000, C438S738000

Reexamination Certificate

active

06399469

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with a notched gate structure by depositing multiple semiconductor layers having different etch rates such that a single patterning and etch process forms the notched gate structure.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, the parasitic capacitance from the overlap of the gate dielectric
116
over the drain extension
104
and the source extension
106
(i.e., the “Miller capacitance) becomes significant in limiting the speed performance of the MOSFET
100
, as known to one of ordinary skill in the art of electronics. Thus, a mechanism is desired for minimizing the overlap of the gate dielectric over the drain extension and the source extension in a MOSFET having scaled down dimensions of tens of nanometers.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a notched gate structure is formed with a first gate structure disposed below a second gate structure. The first gate structure is formed to have a smaller length than that of the second gate structure, and the gate dielectric is formed to have the smaller length of the first gate structure to minimize the overlap of the gate dielectric over the drain and source extensions of the MOSFET. In addition, multiple semiconductor layers having different etch rates are deposited for forming the first and second gate structures such that a single patterning and etch process forms the notched gate structure.
In one embodiment of the present invention, for fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric layer is deposited on the semiconductor substrate. A first semiconductor layer of a first semiconductor material is deposited on the gate dielectric layer, and a second semiconductor layer of a second semiconductor material is deposited on the first semiconductor layer. A photoresist layer is deposited and patterned on the second semiconductor layer to form a gate photoresist structure on the second semiconductor layer. The gate photoresist structure is disposed over the active device area of the semiconductor substrate. Exposed regions of the second semiconductor layer and the first semiconductor layer are etched continuously using a predetermined etch process to form a first gate structure from etching of the first semiconductor layer and to form a second gate structure from etching of the second semiconductor layer. The second gate structure is disposed on the first gate structure.
The first semiconductor material is different from the second semiconductor material. A first etch rate of the first semiconductor material in the predetermined etch process is faster than a second etch rate of the second semiconductor material in the predetermined etch process such that a first length of the first gate structure is smaller than a second length of the second gate structure after the predetermined etch process. Thus, the sidewalls of the first gate structure are disposed inward from the sidewalls of the second gate structure by a predetermined notch distance such that the first gate structure and the second gate structure form a notched gate structure of the field effect transistor.
The present invention may be used to particular advantage when the first semiconductor material is comprised of polysilicon and germanium with a germanium content in a range of from about 30% to about 50%, and when the second semiconductor material is comprised of polysilicon. In that case, the content of germanium in the first semiconductor layer may be raised to increase the predetermined notch distance since a higher content of germanium in the first semiconductor layer increases the first etch rate of the first semiconductor layer. Furthermore, the thickness of the first semiconductor layer may be raised to increase the predetermined notch distance since a longer time for etching a thicker first semiconductor layer also further etches the first semiconductor layer laterally.
In another aspect of the present invention, exposed regions of the gate dielectric layer are etched to form a gate dielectric under the first gate structure such that the gate dielectric has the first length of the first gate structure. A drain extension junction and a source extension junction are formed by implanting an extension dopant in exposed regions of the active device area of the semiconductor substrate.
The extension dopant during the implant is directed vertically perpendicular to the semiconductor substrate with the second gate structure blocking the extension dopant such that the drain extension junction and the source extension junction do not extend under the gate dielectric after the implant. A RTA (rapid thermal anneal) is performed to active the extension dopant in the drain extension junction and the source extension junction. The extension dopant in the drain extension junction and the source extension junction thermally diffuses during the RTA (rapid thermal anneal) such that the drain extension junction and the source extension extend under the gate dielectric after the RTA (rapid thermal anneal).
In this manner, the overlap of the gate dielectric over the drain and source extensions is minimi

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