Fabrication of a field effect transistor with minimized...

Details Fabrication of a field effect transistor with minimized... Fabrication of a field effect transistor with minimized...

2001-05-01

2002-09-10

Niebling, John F. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S216000, C438S289000, C438S301000

Reexamination Certificate

active

06448613

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a method for fabricating a field effect transistor with minimized parasitic Miller capacitance between the gate and the drain and/or between the gate and the source of the field effect transistor.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow doped junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be a polysilicon gate. A gate silicide
120
is formed on the polysilicon gate
118
for providing contact to the polysilicon gate
118
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the polysilicon gate
118
and the gate oxide
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the polysilicon gate
118
and the gate oxide
116
.
Referring to
FIG. 1
, a drain overlap
130
is formed by the drain extension
104
extending under the gate structure
118
, and a source overlap
132
is formed by the source extension
106
extending under the gate structure
118
. The drain overlap
130
is advantageous for lowering the series resistance between the gate and the drain of the MOSFET
100
, and the source overlap
132
is advantageous for lowering the series resistance between the gate and the source of the MOSFET
100
.
However, the drain overlap
130
is disadvantageous because a parasitic Miller capacitance results between the gate and the drain of the MOSFET
100
from the overlap of the gate structure
118
and the gate dielectric
116
over the drain extension
104
. Similarly, the source overlap
132
is disadvantageous because a parasitic Miller capacitance results between the gate and the source of the MOSFET
100
from the overlap of the gate structure
118
and the gate dielectric
116
over the source extension
106
.
Although the dimensions of the MOSFET
100
, such as the channel length, may further be scaled down to tens of nanometers, the drain overlap
130
and the source overlap
132
are typically not scaled down accordingly because a minimum amount of the drain overlap
130
and the source overlap
132
is desired for maintaining a relatively low series resistance between the gate and the drain and between the gate and the source of the MOSFET
100
. However, as the dimensions of the MOSFET
100
are further scaled down and as the drain overlap
130
and the source overlap
132
are not scaled down accordingly, the parasitic Miller capacitance formed by the drain overlap
130
and the source overlap
132
becomes a predominant factor in degrading the device speed of the MOSFET
100
.
Thus, a process is desired for fabricating a MOSFET with drain overlap and source overlap to maintain a low series resistance between the gate and the drain and between the gate and the source of the MOSFET, while at the same time minimizing the parasitic Miller capacitance formed by the drain overlap and/or the source overlap.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a field effect transistor is fabricated to have a drain overlap and a source overlap with reduced parasitic Miller capacitance by creating a depletion region at the sidewalls of a gate structure of the field effect transistor.
In one embodiment of the present invention, a field effect transistor with minimized parasitic Miller capacitance is fabricated within an active device area of a semiconductor substrate. A gate structure is formed on a gate dielectric on the semiconductor substrate over a portion of the active device area, and the gate structure is doped with a first type of dopant. A drain extension is formed within an exposed portion of the active device area of the semiconductor substrate on a drain side of the gate structure. The drain extension has a drain overlap that extends under the gate structure. The sidewall of the gate structure at the drain side of the gate structure is doped with a second type of dopant that is opposite to the first type of dopant. The second type of dopant forms a depletion region from the sidewall at the drain side of the gate structure into approximately an edge of the drain overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap.
The present invention may be used to particular advantage when the parasitic Miller capacitance between the gate and the source of the field effect transistor is also minimized. In that case, a source extension is formed within an exposed portion of the active device area of the semiconductor substrate on a source side of the gate structure. The source extension has a source overlap that extends under the gate structure. The sidewall of the gate structure at the source side of the gate structure is doped with the second type of dopant that is opposite to the first type of dopant. The second type of dopant forms a depletion region from the sidewall at the source side of the gate structure into approximately an edge of the source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the source overlap.
The first type of dopant is an N-type dopant, and the second type of dopant is a P-type dopant, for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the first type of dopant is a P-type dopant, and the second type of dopant is an N-type dopant, for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).


REFERENCES:
patent: 5314834 (1994-05-01), Mazure et al.
patent: 5482871 (1996-01-01), Pollack
patent: 5970353 (1999-10-01), Sultan
patent: 5977591 (1999-11-01), Fratin et al.
patent: 5998272 (1999-12-01), Ishida et al.
patent: 6008099 (1999-12-01), Sultan et al.
patent: 6093610 (2000-07-01), Rodder
patent: 6160299 (2000-12-01), Rodder
patent: 6194748 (2001-02-01), Yu
patent: 6200869 (2001-03-01

Affiliated with

Also associated with

Rating

Fabrication of a field effect transistor with minimized... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of a field effect transistor with minimized..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of a field effect transistor with minimized... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2900388