Fabrication of 3-D capacitor with dual damascene process

Details Fabrication of 3-D capacitor with dual damascene process Fabrication of 3-D capacitor with dual damascene process

2001-09-27

2004-09-14

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000, C438S696000, C438S700000, C438S702000

Reexamination Certificate

active

06790780

ABSTRACT:

FIELD OF INVENTION
The invention relates to the field of capacitors in an integrated circuit.
PRIOR ART
On-chip decoupling capacitors are helpful in compensating for the voltage drop associated with power grid inductance, particularly for high surge current conditions. The inclusion of these capacitors on-chip as opposed to off-chip greatly reduces the affects of the inductance and provides decoupling for higher frequency noise.
In many current semiconductor processes, copper is used as an interconnect material. Often a damascene or dual damascene process is used to form the copper interconnects because of the difficulty in etching copper. As will be seen, the present invention lends itself to fabricating capacitors in conjunction with a dual damascene process.
A dual damascene process for fabricating copper interconnects is disclosed in U.S. patent application Ser. No. 09/746,035, entitled “Method for Making A Dual Damascene Interconnect Using a Multilayer Hard Mask,” filed Dec. 22, 2000 and assigned to the assignee of the present application.


REFERENCES:
patent: 6166423 (2000-12-01), Gambino et al.
patent: 6239021 (2001-05-01), Pramanick et al.
patent: 6320244 (2001-11-01), Alers et al.
patent: 6346741 (2002-02-01), Van Buskirk et al.

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