Fabrication method to approach the conducting structure of a...

Details Fabrication method to approach the conducting structure of a... Fabrication method to approach the conducting structure of a...

1999-04-14

2001-06-19

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S734000, C257S908000

Reexamination Certificate

active

06249018

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for achieving a multilevel contact structure, which is used in the manufacture of integrated circuits, and more specifically, to a conducting structure applied in a DRAM cell.
BACKGROUND OF THE INVENTION
The provision of interconnections in the design of a COB (capacitor over bit line) cell of DRAM is particularly important. In the conventional design, a bit line is twisted to allow the capacitor to contact the substrate.
FIG. 1
illustrates such a conventional design. An active area
100
is formed over a substrate. A contact hole
110
is subsequently formed over portions of the active area
100
. Then, a bit line contact
120
is aligned with and formed over the contact hole
110
. Finally, a bit line
130
is formed on the bit line contact
120
. Portions of the bit line
130
overlap with the bit line contact
120
to form electrical interconnections and than turn back to an off-axis position of active area as bypassing the node contact plug to leave a enough isolation spacing from the node contact. The path of the bit line
130
is thus twisted as a consequence.
The provision of bit lines that are twisted, rather than substantially straight, results in many disadvantages. Series resistance and parasitic capacitance degrade the bit signal as well as raise the resolution and overlay difficulties in wafer processing steps. One possible solution to this limitation could be to twist the orientation of the active area instead of the bit line. However, such a design induces other processing or material issues that still more involving in device manufacturing.
As the urge for higher packing density of DRAM, the planner dimension (or area) of the unit cell keeps going to smaller and smaller via the advances in the lithographic system and the self aligned contact (SAC) technology. However, because of the tolerance of isolation thickness in SAC etching as well as the polishing level variation in CMP planarization, a definite height in vertical is still in need. The aspect ratio of the cell node contact ( or bit line contact in CUB cell) goes still worse and worse. This makes the reliability of the contact resistance and/or the substrate damage become uncontrollable. A two-step contact structure, which uses projected landing pads or recessed landing plugs raised from substrate as step buffering for the second contact forming steps, has been undertaken commonly by most of the DRAM chip supplier.
SUMMARY OF THE INVENTION
In this disclosure, substrate contact landing plugs with off-axis landing sites is achieved by using a novel integrated process. So the aspect ratio of the node contact can be substantially reduced. By introducing one more lithographic layer of isolated hole, we can use the simplest and most reliable patterns of piecewise straight active area, unit sized plug contact and substantially straight bit line layouts, with the least cost in processing steps and slightest resultant surface fluctuation.
For approaching the conducting structure, a conventional COB cell with piecewise straight active areas is used as an illustration. After the accomplishment of the processing steps of the access device, a first dielectric layer is deposited. A contact pattern is then formed on the first dielectric layer for exposing the surface of substrate both at the node contact and bit line contact area, by using a first photoresist layer as a mask to etch the first dielectric layer. This is usually a SAC process that the contacts are self aligned to the substrate as etched. An offset landing plug pattern is then defined by a photoresist-clear pattern only beside the contact pattern at the bit line contact area and recess-etched to an extent into the first dielectric layer, so as to electrically connect with the primary contact structure at the bit line contact site finally. The contact structure is then formed by a deposition-etched process, which performs as a landing plug for the upper contact structures. The top area of the landing plug is thus defined via the additive pattern of the primary contact as well as the offset landing plug pattern. A second dielectric layer is then deposited on the first dielectric layer and the contact structure. Thereafter, a bit line contact pattern is defined by a third photoresist layer. The bit line contact is just located at the position of the offset landing plug and etched to its top, thereby, providing a capability of forming a substantially straight bit line passing over the bit line contact, which is electrically connected with the active area through the bit line contact and the landing plug contact structure.


REFERENCES:
patent: 5654567 (1997-08-01), Numata et al.
patent: 5671175 (1997-09-01), Liu et al.
patent: 5753949 (1998-05-01), Honma et al.

Affiliated with

Also associated with

Rating

Fabrication method to approach the conducting structure of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication method to approach the conducting structure of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method to approach the conducting structure of a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2486218