Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-28
2004-04-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S677000, C438S687000, C438S622000, C438S628000, C438S626000, C438S710000, C257SE21576, C257SE21579, C257SE21584, C257SE21582
Reexamination Certificate
active
06723631
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of fabrication of a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique applicable effectively to a method of fabrication of a semiconductor integrated circuit device having buried interconnects with copper in the main conductor layers thereof.
In semiconductor integrated circuit devices, electronic devices, etc., a technique has been established to form interconnects as an interconnect-forming technology, wherein a conductor film, e.g., aluminum or tungsten, is deposited on an insulation film, and then the film is patterned by the usual photolithography and dry-etch technique, thereby being formed into an interconnect.
In the above interconnect-forming technique, however, there is a conspicuous increase in interconnect resistance resulting from scale-down of the devices and interconnects forming semiconductor integrated circuit devices or the like, resulting in occurrence of an interconnect delay, Thus, there is a limitation to further improvement in the performance of a semiconductor integrated circuit device or the like. For this reason, in recent years studies have been made on an interconnect-forming technology called “damascene”, for example. The damascene technology can be roughly divided into a single-damascene technique and a dual-damascene technique.
The single damascene technique is a method in which, after forming an interconnect trench in an insulation film, a main conductor layer for interconnect formation is deposited in the interconnect trench; and, then, the main conductor layer is polished so as to be left only at the inside of the interconnect trench, using chemical mechanical polishing (CMP), for example, thereby forming a buried interconnect at the inside of the interconnect trench.
Meanwhile, the dual damascene technique is a method in which, after forming an interconnect trench and a hole for connection to the lower-leveled interconnect in an insulation film, a main conductor layer for interconnect formation is deposited on the insulation film and in the interconnect trench and hole; and, then, the main conductor layer is polished so as to be left only at the inside of the interconnect trench and hole, using CMP or the like, thereby forming a buried interconnect at the inside of the interconnect trench and hole.
In any of the techniques, the interconnect main conductor material comprises, for example, a low-resistance material, such as copper, from a viewpoint of improving the performance of the semiconductor integrated circuit device or the like. Copper, having the advantage of lower resistance and greater allowable current in reliability by two orders of magnitude than that of aluminum, requires a smaller film thickness for the same interconnect resistance, and, hence, results in a reduced capacitance between adjacent interconnects.
However, copper tends to more readily diffuse into an insulation film as compared to other metals, such as aluminum and tungsten. For this reason, it is considered that, when using copper as an interconnect material, there is a need to form a copper-diffusion-preventing thin conductive barrier film on a surface of a copper main-conductor layer (bottom and side surfaces), i.e. on an inner wall of the interconnect trench. Meanwhile, there is a technique in which a cap film, for example, of silicon nitride, is deposited over the entire upper surface of an insulation film formed with an interconnect trench in a manner covering the upper surface of a buried interconnect, thereby preventing copper in the buried interconnect from diffusing into the insulation film through the upper surface of the buried interconnect.
The buried interconnect technology having a copper main-conductor layer is described, for example, in JP-A-11-330246. This technique is such that, after forming a copper interconnect in an interconnect opening formed in a dielectric layer, a barrier layer is formed; and, then, a plasma process is carried out using only ammonia as a source gas, thereby improving the adhesion between the copper interconnect and the copper barrier layer. Meanwhile, JP-A-11-16912, for example, discloses a technique to eliminate an oxide layer formed in an interconnect part exposed at a bottom of a connection hole by carrying out a heat plasma or ultraviolet-ray illumination process in a deoxidizing atmosphere.
Meanwhile, a post-CMP cleaning technique is described, for example, in “Monthly Semiconductor World, published October 1998” Sep. 20, 1998, by Press Journal, pp 62-72.
SUMMARY OF THE INVENTION
According to the result of study by the present inventors, it has been found that the following problems are inherent in the buried interconnect technique using copper in a main conductor layer thereof.
Firstly, there exists a problem in that, when using copper as an interconnect material, the TDDB (Time Dependence on Dielectric Breakdown) life is conspicuously short as compared to other metal materials (e.g. aluminum, tungsten). Moreover, in addition to the scale-down in interconnect pitch and the trend toward increasing the effective electric field intensity, there is a recent tendency to use, as an interlevel insulation film, an insulation material having a lower dielectric constant than that of silicon dioxide, in view of the decreasing interconnect capacitance. However, because the low-dielectric-constant dielectric material generally is low in dielectric strength, there is still more difficulty in securing sufficient a TDDB life.
Incidentally, a TDDB test is one of the acceleration test methods used to determine an interlevel dielectric breakdown strength, i.e., a test method for presuming a dielectric breakdown time (life) in the usual-use environment from a time until dielectric breakdown under a high electric field at a predetermined temperature higher than that in the usual-use environment. The TDDB life is a life to be presumed from such a TDDB test. The TDDB life will be referred to later.
Secondly, if a silicon nitride film is used as a cap film on a buried interconnect having a copper main-conductor layer, silicide or copper oxide is formed at the interface of the copper and the silicon nitride film during formation of a cap film, causing a problem of increased resistance of the buried interconnect. The experiment by the present inventors has first found that such silicide or copper oxide is one of the major causes of copper diffusion, as will be referred to later.
Thirdly, there is a problem in that strip-off occurs between the interconnect layer of the buried interconnect and an insulation film (e.g. the cap film) formed in the upper level thereof.
Fourthly, there is a problem in that the interconnect resistance increases due to the cleaning process after a CMP process for forming a buried interconnect (hereinafter, referred also to as post-CMP cleaning). It has been found that this problem is particularly conspicuous where a buried interconnect is formed by a plating method.
It is an object of the invention to provide a technique which is capable of improving the dielectric breakdown strength between interconnects having copper in the main conductor layers thereof.
Another object of the invention is to provide a technique which is capable of preventing an increase in the resistance of an interconnect having copper main-conductor layer.
Another object of the invention is to provide a technique to improve the adhesion between an interconnect having a copper main conductor layer and a cap film.
The foregoing and other objects and novel features of the invention will be made apparent from the following description in the present Specification and the appended drawings.
The aspects of the invention as disclosed in the present Application, briefly explained as a summary of representative features thereof, include the following.
Namely, the method of the present invention includes a step of carrying out a plasma process on a semiconductor substrate in a hydrogen gas atmosphere and a step of carrying out a plasma process o
Asaka Shoji
Konishi Nobuhiro
Maruyama Hiroyuki
Noguchi Junji
Ohashi Naohumi
Antonelli Terry Stout & Kraus LLP
Keshavan Belur V
Renesas Technology Corporation
Smith Matthew
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