Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-07-31
2007-07-31
Kebede, Brook (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C257SE21237, C257SE21304
Reexamination Certificate
active
11167253
ABSTRACT:
A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
REFERENCES:
patent: 5868857 (1999-02-01), Moinpour et al.
patent: 5874778 (1999-02-01), Bhattacharyya et al.
patent: 5901399 (1999-05-01), Moinpour et al.
patent: 5976267 (1999-11-01), Culkins et al.
patent: 6059889 (2000-05-01), Jensen et al.
patent: 6150696 (2000-11-01), Iwamatsu et al.
patent: 6159081 (2000-12-01), Hakomori
patent: 6232201 (2001-05-01), Yoshida et al.
patent: 6261953 (2001-07-01), Uozumi
patent: 6267649 (2001-07-01), Lai et al.
patent: 6309981 (2001-10-01), Mayer et al.
patent: 6334229 (2002-01-01), Moinpour et al.
patent: 6361708 (2002-03-01), Kubo et al.
patent: 6376363 (2002-04-01), Iguchi
patent: 6482749 (2002-11-01), Billington et al.
patent: 6509270 (2003-01-01), Held
patent: 6683007 (2004-01-01), Yamasaki et al.
patent: 6924236 (2005-08-01), Yano et al.
patent: 2001/0024691 (2001-09-01), Kimura et al.
patent: 2001/0051432 (2001-12-01), Yano et al.
patent: 2002/0006876 (2002-01-01), Hongo et al.
patent: 1 167 583 (2002-01-01), None
patent: 1 174 912 (2002-01-01), None
patent: 64-71656 (1989-03-01), None
patent: 4-034931 (1992-02-01), None
patent: 5-41449 (1993-02-01), None
patent: 09-186234 (1997-07-01), None
patent: 10-296641 (1998-11-01), None
patent: 10-309666 (1998-11-01), None
patent: 10-328989 (1998-12-01), None
patent: 11-033888 (1999-02-01), None
patent: 11-045868 (1999-02-01), None
patent: 11-048109 (1999-02-01), None
patent: 11-090803 (1999-04-01), None
patent: 11-104942 (1999-04-01), None
patent: 2000-021882 (2000-01-01), None
patent: 2000-68273 (2000-03-01), None
patent: 2000-77414 (2000-03-01), None
patent: 2000-173885 (2000-06-01), None
patent: 2001-77113 (2001-03-01), None
Official Action from the Japanese Patent Office, for Japanese Patent Application No. 2001-118413, dated Jan. 30, 2007.
Arai Toshiyuki
Kanai Fumiyuki
Kawai Ryousei
Nakabayashi Shinichi
Tsuchiyama Hirofumi
Kebede Brook
Renesas Technology Corp.
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