Fabrication method of semiconductor integrated circuit device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C438S664000, C438S683000

Reexamination Certificate

active

10733377

ABSTRACT:
A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. More specifically, a low resistance source and drain (n+type semiconductor regions, p+type semiconductor regions) with less junction leakage current are formed, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+type semiconductor regions, p+type semiconductor regions) of the MISFET, by depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (Co2Si) layer to a cobalt monosilicide (CoSi) layer and, then, to a cobalt disilicide (CoSi2) layer, successively.

REFERENCES:
patent: 6117771 (2000-09-01), Murphy et al.
patent: 6136699 (2000-10-01), Inoue
patent: 6221764 (2001-04-01), Inoue
patent: 6337272 (2002-01-01), Hamanaka
patent: 6440851 (2002-08-01), Agnello et al.
patent: 11-283935 (1999-10-01), None
patent: 2000-243726 (2000-09-01), None
Chinese Official Action, for Application No. 200310118530.8, dated Apr. 28, 2006.

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