Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-02-02
2001-04-24
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S255000, C438S396000
Reexamination Certificate
active
06221730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device equipped with a semiconductor layer with a hemispherical-grained (HSG) configuration, which is preferably applied to fabrication of dynamic random-access memories (DRAMs) necessitating very large capacitance.
2. Description of the Prior Art
In recent years, to raise the integration level of electronic elements in DRAMs, there has been the strong need to increase the capacitance per chip area of memory cell capacitors. To cope with this need, the top or bottom electrode of each memory cell capacitor has been formed to have a solid or three-dimensional shape such as a cylinder.
Moreover, to increase the surface area of the bottom electrode, the use of a silicon (Si) layer with a HSG configuration (i.e., a HSG Si layer) has been studied to increase the surface irregularities of the bottom electrode, thereby roughening positively the surface of the bottom electrode. In this case, however, if the HSG Si layer is depleted during operation of the memory cell capacitor, the electric resistance of the HSG Si layer increases, which means that any satisfactory capacitance increase is unable to be realized. As a result, it has been usual that a suitable impurity or dopant such as phosphorus (P) is introduced into the HSG Si layer by a conventional diffusion or ion-implantation process, thereby lowering the electric resistance of the HSG Si layer.
Japanese Non-Examined Patent Publication No. 9-289292 published in November 1997 discloses fabrication methods of a semiconductor device equipped with a surface-roughened polysilicon layer similar to the HSG Si layer.
One of these prior-art methods thus disclosed is comprised of a first step of forming an interlayer dielectric layer on or over a semiconductor substrate, a second step of forming a contact hole in the interlayer dielectric layer to uncover the underlying substrate, a third step of forming a surface-roughened polysilicon (poly-Si) layer on the interlayer dielectric layer to cover the contact hole, a fourth step of forming a phosphosilicate glass (PSG) layer on the surface-roughened poly-Si layer, a fifth step of diffusing phosphorus (P) atoms contained in the PSG layer into the surface-roughened poly-Si layer as a dopant, and a six step of removing the PSG layer from the surface-roughened poly-Si layer.
In the fifth step, the diffusion of the P atoms into the surface-roughened poly-Si layer is carried out by a heat treatment process at a comparatively high temperature of approximately 800 to 950° C. for approximately 10 to 60 minutes.
Incidentially, to fabricate a DRAM incorporated with logic circuits, heat treatment processes are necessary to be carried out at a temperature as low as possible for a time as short as possible, thereby preventing the logic circuits (especially, transistors provided in the logic circuits) from being thermally damaged.
With the above-described prior-art fabrication method disclosed in Japanese Non-Examined Patent Publication No. 9-289292, however, the fifth step of diffusing the P atoms into the surface-roughened polysilicon layer is carried out at a high temperature of approximately 800° C. to 950° C. for a long time of approximately 10 to 60 minutes. Therefore, this prior-art method is unable to be applied to fabrication of the DRAM incorporated with the logic circuits.
Also, since the fifth step of diffusing the P atoms into the surface-roughened poly-Si layer is carried out at a high temperature of approximately 800° C. to 950° C. in the prior-art method, the Si atoms existing in the surface-roughened poly-Si layer are likely to be consumed during to the progress of the thermal oxidation of the PSG layer through the fifth step, resulting in a problem that the surface roughness of the surface-roughened poly-Si layer is decreased.
As described above, in fabrication of a DRAM incorporated with logic circuits, the protection of the logic circuits and the prevention of the surface-roughness decrease of the surface-roughened poly-Si layer are in a trade-off relationship with the suitable doping or introduction of the dopant into the surface-roughened poly-Si layer.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention to provide a fabrication method of a semiconductor device that makes it possible to introduce suitably a dopant into surface grains of a semiconductor layer at a comparatively low temperature.
Another object of the present invention to provide a fabrication method of a semiconductor device that makes it possible to introduce a dopant into a surface-roughened semiconductor layer while protecting logic circuits incorporated into a semiconductor memory device from applied heat.
Still another object of the present invention to provide a fabrication method of a semiconductor device that suppresses the surface roughness of a semiconductor layer with surface grains to be decreased in a heat-treatment process for introducing a dopant into the grains.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A fabrication method of a semiconductor device according to the present invention is comprised of the following first to third steps.
In the first step, a first semiconductor layer is formed over a semiconductor substrate through a first dielectric.
In the second step, the first semiconductor layer is heat-treated to form semiconductor grains on a surface of the first semiconductor layer, thereby roughening the surface of the first semiconductor layer. The grains are made of a same material as that of the first semiconductor layer.
In the third step, the first semiconductor layer with the semiconductor grains is heat-treated at a temperature of approximately 700° C. to 780° C. for a specific time in an atmosphere containing a gaseous dopant, thereby introducing the dopant into the semiconductor grains of the first semiconductor layer from the atmosphere.
With the fabrication method of a semiconductor device according to the present invention, after the semiconductor grains are formed on the surface of the first semiconductor layer in the second step, the dopant is introduced into the semiconductor grains of the first semiconductor layer from the atmosphere containing the gaseous dopant in the third step. This is unlike the previously-described prior-art method in which the dopant is introduced into the surface-roughened semiconductor layer from the adjacent PSG layer.
Therefore, although the third step is carried out at a comparatively low temperature of approximately 700° C. to 780° C., the dopant can be suitably doped into the surface grains of the first semiconductor layer as desired.
Moreover, since the third step is carried out at a comparatively low temperature of approximately 700° C. to 780° C., the dopant can be introduced into the surface-roughened first semiconductor layer while protecting logic circuits incorporated into the semiconductor memory device from the heat applied in the third step.
The reason why the third step is carried out at a temperature of approximately 700° C. to 780° C. is as follows.
If the temperature is lower than 700° C., the necessary time for the heat-treatment process needs to be excessively long to realize a desired dopant concentration of the semiconductor grains, which is unable or difficult to be practically used. If the temperature is higher than 780° C., the electronic elements such as transistors incorporated into the semiconductor memory device are likely to be badly affected by the heat applied in the third step. For example, the withstand voltage and/or mutual conductance characteristics of the incorporated transistors are degraded due to profile deviation of the semiconductor regions or the like.
In a preferred embodiment of the method according to the present invention, the specific time in the third step is approximately 10 minutes to 120
Hayes Soloway Hennessey Grossman & Hage PC
Jr. Carl Whitehead
NEC Corporation
Thomas Toniae M.
LandOfFree
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