Fabrication method of semiconductor device

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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Details

C438S706000, C438S712000, C257SE21170, C257SE21218, C257SE21227, C257SE21304, C257SE21546

Reexamination Certificate

active

07462562

ABSTRACT:
Fabrication method of semiconductor device to reduce leak current at junction interface of p-type well and n-type well. The method includes forming a first trench portion by selective dry etching of a silicon substrate using a first etching gas and forming a second trench portion including an enlarged width portion downward from a bottom of the first trench portion by additional dry etching of a silicon substrate at the bottom of the first trench portion using a second etching gas. A mixture gas of a chlorine gas and a fluorocarbon gas is used as the second etching gas and also a bias voltage lower than that in the process to form the first trench portion are used in the process to form the second trench portion.

REFERENCES:
patent: 2001/0023960 (2001-09-01), Soga et al.
patent: 2006/0087000 (2006-04-01), Okuno
patent: 2001-244325 (2001-09-01), None
patent: 2002-43413 (2002-02-01), None
patent: 2002-184856 (2002-06-01), None

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