Fabrication method of multi-domain vertical alignment pixel...

Details Fabrication method of multi-domain vertical alignment pixel... Fabrication method of multi-domain vertical alignment pixel...

2009-05-27

2010-10-12

Dang, Phuc T (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S034000, C438S149000, C234S043000, C234S054000, C257S059000, C257S072000

Reexamination Certificate

active

07811869

ABSTRACT:
A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.

REFERENCES:
patent: 2006/0267016 (2006-11-01), Ahn et al.
patent: 2008/0088783 (2008-04-01), Tai et al.
patent: 2008/0121885 (2008-05-01), Kuo

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