Fabrication method of a twin-tub capacitor

Details Fabrication method of a twin-tub capacitor Fabrication method of a twin-tub capacitor

1999-06-04

2001-03-06

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S254000, C438S255000, C438S396000, C438S398000

Reexamination Certificate

active

06197652

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106001, filed Apr. 15, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a capacitor for a semiconductor memory cell, and more particularly, relates to fabrication method of a twin-tub capacitor for a DRAM (Dynamic Random Access Memory) cell.
2. Description of the Related Art
As the dimensions of semiconductor devices are being scaled down to a deep sub-micron level, the size of the capacitor in a DRAM cell is also being reduced. Since the capacitance is proportional to the surface area of the capacitor, as the area of a memory cell decreases, the capacitance of the capacitor tends to decrease, thereby lowering the performance of the memory cells. On the other hand, the advances in computer applications have increased the demand for high capacity memory chips. Thus, the demand of decreasing the size of the memory cells while simultaneously increasing the memory chip capacity has altered the direction of the advancements of the fabrication of a DRAM memory cell capacitor.
For a semiconductor memory cell capacitor, reducing the dielectric layer thickness, substituting with high dielectric constant materials and increasing the capacitor surface area are the three methods generally used to increase a cell capacitance. Among the three methods, reducing the dielectric layer thickness and increasing the dielectric constant pose technical challenges, especially in mass productions where the reliability of the device and the yield risks may be affected. Thus, increasing the surface area of a capacitor is the preferred approach to increase the capacitance in a limited cell size.
Currently, the surface area of a capacitor is increased by means of the hemispherical grain (HSG) technology or changing the capacitor surface. The HSG process is popular and widely used in the semiconductor field; however, the equipment for the process is more expensive compared to the traditional low pressure chemical vapor deposition (LPCVD) furnace. Furthermore, the HSG growth process is complicated and vulnerable to variations, compared to changing the capacitor structure, which is simple and easy to manipulate.
FIGS. 1A
to
1
C are cross-sectional views of the conventional stack, crown and twin-tub capacitors.
According to
FIGS. 1A
to
1
C, the stack
100
and crown
102
capacitors are the two most frequently used structures for a DRAM cell application. Between these two capacitors, the crown capacitor
102
is preferred because of the extra surface area from its inner wall.
The more advanced twin-tub capacitor
104
comprises even more inner walls than that of the crown capacitor
102
. Hence, the twin-tub capacitor
104
has the most surface areas among the three types of capacitor, and is the most appropriate type of capacitor to meet the current trend of having a high capacity memory with a reduced cell size.
Related activities in the manufacturing of a twin-tub capacitor can be referred to U.S. Pat. Nos. 5,652,165 and 5,721,154.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a fabrication method for a twin-tub capacitor within increased surface area.
The current invention provides a fabrication method of a twin-tub capacitor comprises the following steps. A substrate is provided. A first dielectric layer is formed to cover the substrate, followed by a deposition of an etching stop layer on the first dielectric layer. A contact window is etched in the etching stop layer and the first dielectric layer. Consequently, a first conductive layer is deposited, covering the etching stop layer and filling in the contact window. The first conductive layer is defined, and then deposited over by a layer of a second dielectric layer. Thereafter, the second dielectric layer is defined to form a plurality of column structures. A second conformal conductive layer is deposited on the surface of the column structures, followed by a removal of the second conductive layer located on the top surface of the column structures. After which, the column structures are removed.
The current invention uses a dielectric layer to form a multiple column structures, followed by forming a conductive layer to cover the column structures. A chemical mechanical polish process is conducted to remove the conductive layer located on the top surface of the column structures in order to isolate each capacitor. These column structures are further removed to form a twin-tub capacitor.
This invention uses the current semiconductor fabrication techniques. The entire process is simple and easy to apply to the fabrication of a DRAM cell.
The current invention provides a twin-tub capacitor with an increased surface area, thereby increasing the capacitance of the device.
This invention further discloses that a simultaneous application of a hemispherical grain technique and a twin-tub structure enhances the development of a high capacitance capacitor, which is consistent with the current development trend of a semiconductor device.


REFERENCES:
patent: 5468670 (1995-11-01), Ryou
patent: 5650351 (1997-07-01), Wu
patent: 5652165 (1997-07-01), Lu et al.
patent: 5721154 (1998-02-01), Jeng
patent: 5759895 (1998-06-01), Tseng
patent: 5789290 (1998-08-01), Sun

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