Fabrication method for semiconductor integrated devices

Details Fabrication method for semiconductor integrated devices Fabrication method for semiconductor integrated devices

2002-03-21

2004-06-01

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S778000, C438S680000, C438S686000, C438S681000

Reexamination Certificate

active

06743739

ABSTRACT:

CLAIM OF PRIORITY
The present invention claims priority to Japanese Patent Application No. 2001-086930 filed on Mar. 26, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to processes for fabricating semiconductor devices with a high dielectric constant capacitor.
2. Description of the Background
Semiconductor devices such as dynamic random access memories (DRAM) have achieved high capacity through reduction in the cell area. An inevitable consequence of this reduction is a decrease in the area available for capacitors. Nevertheless, it is still essential for a semiconductor device to store a certain amount of stored charge necessary for memory reading without soft errors. In other words, for high capacity semiconductor devices, it is necessary to provide some means by which to increase the amount of stored charge per unit area. One way to address this need is to form the capacitor insulating film from an oxide dielectric material having a high dielectric constant.
A conventional capacitor insulating film used for memory LSI (Large Scale Integration) is SiO
2
film (with a dielectric constant of 3.8) or Si
3
N
4
film (with a dielectric constant of 7 to 8). There materials are currently being replaced by Ta
2
O
5
film (with a dielectric constant higher than 20). To store a much larger amount of charge, it has been proposed to form the capacitor insulating film from an oxide dielectric material having a dielectric constant greater than 100, as exemplified by strontium titanate (SrTiO
3
, “STO” for short), barium strontium titanate ((Ba,Sr)TiO
3
, “BST” for short), lead titanate zirconate (Pb(Zr,Ti)
3
, “PZT” for short), or bismuth-based laminar ferroelectrics. However, these oxide dielectric materials (including Ta
2
O
5
) have the disadvantage of requiring post heat treatment at high temperatures (e.g., 300-700° C.) in an oxidizing atmosphere to obtain these improved electrical properties. This heat treatment typically causes the lower electrode to be oxidized by oxygen in the oxidizing atmosphere, which may result in an insulating film having a lower dielectric constant than the capacitor insulating film. Consequently, there may be a substantial decrease in the capacity of capacitor.
A promising way to address this problem is to form the lower electrode from platinum (Pt), ruthenium (Ru), iridium (Ir), or the like. Pt is comparatively stable when subjected to a high temperature and oxidizing atmosphere. Ru and Ir retain electrical conductivity even after oxide formation. Of these materials, Ru is suitable for microfabrication and is the most desirable as the lower electrode for oxide dielectric material. In addition, a Ru electrode has a large work function and prevents leakage current due to the height of the Schottky barrier at the interface between the capacitor insulating film and the electrode. Therefore, Ru is also a promising material for the upper electrode.
Even though capacitors on a memory LSI of Giga-bit scale may be formed from the Ru electrode and the above-mentioned oxide dielectric material, it is not conventionally possible to secure the amount of stored charge necessary for reading because the area for capacitors is too small. Thus, there arises a need to make the capacitor three-dimensional in order to substantially increase the capacitor area. One way to address this need requires the several steps of: (1) forming a three-dimensional lower electrode from Ru; (2) forming an oxide dielectric material as a capacitor insulating film; and (3) forming an upper electrode from Ru on the oxide dielectric material. These steps essentially involve chemical vapor deposition to form the Ru electrodes.
An exemplary process for forming a Ru film by chemical vapor deposition from an organoruthenium compound as a precursor is described in
Japanese Journal of Applied Physics,
38 (1999), p. 2194. This process uses bis(cyclopentadienyl) ruthenium (Ru(C
5
H
5
)
2
) as a raw material to form the Ru film.
The three-dimensional lower and upper electrodes are preferably formed by making deep holes in the surface of silicon oxide film (which permits easy microfabrication) and subsequently depositing Ru by chemical vapor deposition. This procedure may involve the problems explained below with reference to
FIG. 11
(a sectional view).
It is assumed that a plug
1
of titanium nitride and an insulating interlayer
2
of SiO
2
(in the plug area) have been formed. The procedure starts with depositing a 700-nm thick insulating interlayer
3
of SiO
2
(in the capacitor area). Subsequently, deep holes are formed in the insulating interlayer
3
by well-known photolithography and dry etching techniques such that the bottom of the holes reaches the surface of the insulating interlayer
2
. These holes preferably have a round, elliptical, or rectangular opening. The diameter of the opening is smaller than 130 nm in a memory LSI of Giga-bit scale.
If each capacitor is to have a capacity larger than 30 fF per bit, the insulating interlayer
3
should have a thickness (equivalent to a hole depth) of at least 700 nm, even in the case where the insulating film of BST has a thickness of 0.4 nm in terms of SiO
2
. Thus, the deep hole requires an aspect ratio no smaller than 5, wherein the “aspect ratio” is defined as the ratio of a hole depth to an opening diameter. If the capacitor insulating film is formed from Ta
2
O
5
with a thickness of 0.8 nm in terms of SiO
2
, then the insulating interlayer
3
needs to be thicker than 1500 nm or the hole needs to be deeper than 1500 nm (with an aspect ratio of 11 at least). In this deep hole is formed the lower ruthenium electrode
10
(20 nm thick) by chemical vapor deposition. See, FIG.
11
(
a
).
Several potential problems as pointed out below are involved in the conventional chemical vapor deposition from an organoruthenium compound as a precursor. According to the above-mentioned paper, the procedure uses bis(cyclopentadienyl) ruthenium (C
5
H
5
)
2
) as a precursor, and the ruthenium film is formed by reactions in two stages. The reaction in the first stage is limited by the surface reaction which has an activation energy of 2.48 eV at a film-forming temperature no higher than 250° C. and at an oxygen partial pressure of 0.07 Torr. As the temperature exceeds 250° C., the reaction in the second stage takes place which is limited by the mass transport. In this second stage, the film forming rate becomes constant at approximately 23 nm/min. This procedure results in such a high conformality so as to form a ruthenium film with a step coverage of nearly 100% in a deep hole (having a diameter of 130 nm and an aspect ratio of 4) at a film-forming temperature of 230° C. Unfortunately, the film-forming rate at 230° C. is only about 2.8 nm/min. Therefore, because it takes about 7 minutes to form a 20-nm thick film, the procedure mentioned above may not be suitable for mass production because of the low throughput. In addition, if the above procedure is to be applied to the capacitors of a Giga-bit DRAM, it should be able to form ruthenium film for the upper electrode in a deep hole having an aspect ratio no smaller than 12, even in a case where BST is used for the capacitor insulating film.
After the ruthenium film has been formed as shown in FIG.
11
(
a
), subsequent steps are carried out in the following manner. The lower electrode which has been deposited on the insulating interlayer
3
is removed by sputter etching so as to electrically isolate adjacent capacitors from each other. Thus, a three-dimensional lower electrode structure is obtained, as shown in FIG.
11
(
b
).
Subsequently, an oxide dielectric material
6
is the deposited by chemical vapor deposition. In the case of BST, the thickness of the deposit is 20 nm. In the case of Ta
2
O
5
, the thickness of deposit is 10 nm. Thereafter, the upper ruthenium electrode
7
is formed by chemical vapor deposition. In this way the capacitor is completed as shown in FIG.
11
(
c
). It is necessary that the upper ruthenium electrode should completely cover th

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