Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-06
2002-06-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S663000, C438S522000, C438S660000, C438S948000, C355S057000, C355S053000, C355S067000
Reexamination Certificate
active
06403475
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to technology for fabricating semiconductor integrated circuit devices and, more particularly, to a technology that can be effectively applied to a semiconductor-manufacturing process for heat-treating wafers based on an RTA (rapid thermal annealing) system using lamps as a heat source.
ULSI Technology (by C. Y. Chang, S. M. Sze, published by McGraw-Hill Co., 1996, pp. 144-204) discloses in detail an RTP (rapid thermal process) for use in the manufacture of semiconductors.
Japanese Patent Laid-Open No. 250633/1987 (Inoue) discloses a halogen lamp annealing device in which a plurality of mat glass plates having a rugged pattern on the surfaces thereof are arranged between a semiconductor wafer and a source of light (halogen lamp). According to this device, light arriving at the wafer from the source of light is scattered in a multiplicity of stages due to the rugged surfaces of the mat glass plates, and the distribution of the intensities of light falling on the wafer surfaces is uniformalized, preventing the occurrence of surface defects on the wafer surfaces and slipping. As the mat glass which is placed between the wafer and the source of light, there can be used a ground glass and a figured glass such as currently available in the market.
Japanese Patent Laid-Open No. 94925/1987 (Ohno) discloses a heat-treating (annealing) device in which a transparent quartz holder for supporting a wafer is covered with a covering film. According to this device, the covering film is first heated by light from a source of light (halogen lamp) and, then, the wafer is heated by light radiated from the covering film. It is claimed that the temperature distribution is uniformalized on the surfaces of the wafer irrespective of the surface condition of the wafer such as a difference in the thickness of the oxide film. The covering film is formed of a heat-resistant material such as titanium (Ti).
Japanese Patent Laid-Open No. 110726/1989 (Yabuki) discloses a lamp annealing method in which an absorbent is arranged on the main surface of the, but a small distance is maintained from the wafer. According to this method, it is claimed that the heat energy of the absorbent heated by the lamp is given to the wafer due to the thermal convection, thereby decreasing dispersion in the heated temperature on the surface of the wafer. The absorbent is formed of silicon carbide (SiC) or a carbon member having a diameter slightly larger than that of the wafer.
Japanese Patent Laid-Open No. 117319/1989 (Kanazawa) discloses a method of forming a shallow impurity-diffused layer on a silicon wafer while maintaining uniformity and reproduciability by using a lamp annealing device instead of using the conventional diffusion furnace. In the chamber of the lamp annealing device used here, a boron plus plate and a PBN plate which are solid sources of diffusion are arranged so as to be opposed to the silicon wafer, and the solid sources of diffusion and the wafer are heated simultaneously and rapidly in a vacuum, so that impurities are diffused in the silicon wafer from the solid sources of diffusion.
Japanese Patent Laid-Open No. 303121/1990 (Karen A. Grim, et al.) discloses a method of effecting rapid thermal annealing (RTA) by accommodating a wafer in a container called a black box. This container is equipped with a lid for sealing a cavity that comprises a base for supporting the wafer and an annular guard ring surrounding the wafer, which container absorbs almost all radiant energy emitted from a halogen lamp which is the source of light, and radiates this energy. It is claimed that when the wafer in which impurity ions are injected is rapidly and thermally annealed in the container, the impurities are activated almost without developing any defect, such as slip lines, on the wafer.
Japanese Patent Laid-Open No. 6018/1991 (Imaizumi) discloses a lamp annealing device in which tungsten-halogen lamps are arranged on both the upper and lower sides of a quartz chamber accommodating a susceptor for placing a wafer, and a plurality of opaque quartz plates at variable angles are arranged between the quartz chamber and the halogen lamp. According to this device, the angles of the opaque quartz plates are changed so that the temperature at the peripheries of the wafer from where heat easily radiates becomes equal to the temperature at the center, thereby improving the uniformity in the distribution of temperatures on the surface of the wafer.
Japanese Patent Laid-Open No. 291170/1993 (Nukii) discloses a lamp annealing device in which a net obtained by knitting a metal wire such as of Ni (nickel) in the form of a grid is arranged between a halogen lamp and a wafer. When the annealing is effected by arranging the net between the wafer and the lamp, the intersecting portions of the metal wires become point sources of light, and it is claimed that the net as a whole works as a plane source of light enhancing the uniformity in the distribution of temperatures on the surface of the wafer.
Japanese Patent Laid-Open No. 232138/1994 (Hisaka) discloses a lamp annealing device equipped with a halogen lamp for heating the whole wafer and an auxiliary heater for heating the peripheries of the wafer. The auxiliary heater comprises carbon heaters or halogen lamps which are arranged to surround the susceptor. According to this device, the power of the auxiliary heater is controlled to adjust the difference of temperature between the peripheries in the wafer and the central portion thereof, making it possible to highly uniformly anneal the wafer without causing distortion.
Japanese Patent Laid-Open No. 321547/1998 (Ishihara, et al.) discloses a heat-treating device in which halogen lamps are provided on the upper surface and on the lower surface of a quartz container for containing the wafer, and heat-equalizer plates are provided on the upper surface side and on the lower surface side of the wafer in the container. The pair of heat-equalizer plates are formed in the shape of a disk and are arranged nearly in parallel with the wafer. One heat-equalizer plate has a diameter larger than that of the wafer and has a circular hole perforated in the central portion thereof. The other heat-equalizer plate has a diameter nearly equal to that of the above heat-equalizer plate (materials of the pair of heat-equalizer plates have not been disclosed). It is claimed that according to this device, dispersion in the temperature distribution is suppressed on the surfaces of the wafer due to the arrangement of the heat-equalizer plates on both sides of the wafer.
In a modern process for fabricating logic LSIs of high performance, the resistance of the Al (aluminum) wiring is increasing and the reliability is decreasing as the wirings are formed ever more finely, accounting for a major factor for impairing the fabrication of LSIs of high performance.
There has been an attempt to employ buried copper wiring formed by the so-called Damascene method by forming wiring grooves (and through holes) in the insulating film deposited on the silicon (Si) substrate, depositing a copper film having an electric resistance smaller than the Al film on the insulating film which includes the interiors of the wiring grooves (and through holes), and removing the unnecessary copper film on the outside of the wiring grooves by a chemical mechanical polishing (CMP) method (Japanese Patent Laid-Open Nos. 278822/1990, 214834/1998, etc.).
Since a suitable source gas has not yet been found, it is at present difficult to form a copper film by the CVD method and, hence, the sputtering method or the plating method has chiefly been used. When the copper film is deposited by sputtering on the insulating film in which the wiring grooves have been formed, the copper film is not buried to a sufficient degree in the wiring grooves. It, therefore, becomes necessary to enhance the fluidity of the copper film by annealing to cause a reflow of the copper film into the wiring grooves. The copper film formed by the plating method, too, must be
Nakatsuka Yasuhiko
Suzuki Tadashi
Tanabe Yoshikazu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Jr. Granvill D
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