Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-03-10
2001-11-13
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S637000, C438S638000, C438S975000
Reexamination Certificate
active
06316328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device including alignment marks for measuring or estimating lithography overlay accuracy, and a fabrication method thereof.
2. Description of the Prior Art
Recently, miniaturization and integration have been progressing more and more. At present, ultra large-scale integrated semiconductor devices (ULSIs), for example, not only 256-Megabit Dynamic-Random-Access Memories (DRAMs) designed according to 0.25 micron design rule, but also 1 Gigabit DRAMs designed according to sub 0.25 &mgr;m design rule, are being developed and examined. In order to deal with this progress in miniaturization and integration, the need for improving or enhancing the pattern-to-pattern (or, mask-to-mask) overlay or registration accuracy in photolithography processes has been becoming greater.
Typically, in semiconductor device fabrication, patterned layers made of metal, semiconductor, dielectric, and so on are successively formed so as to be stacked on a semiconductor substrate, thereby fabricating miniaturized semiconductor devices. In photolithography, it is required that patterns of geometric shapes in an upper level are accurately overlaid with respect to previously defined patterns of geometric shapes in a lower level. The required overlay accuracy for the patterns has been becoming stricter with progressing miniaturization of the semiconductor devices.
Conventionally, two typical measuring methods have been used to measure the overlay or placement error of the patterns. With a first conventional measuring method of this sort, rectangular patterns are formed at a fixed pitch in each layer in each semiconductor chip region. The overlapping or stacking state of the patterns in the two layers gives the degree of overlay error. The rectangular patterns are generally termed the “alignment vernier caliper” or alignment vernier”.
With a second conventional measuring method of this sort, which is typical, a “lower alignment box mark” is formed in a lower layer and an “upper alignment box mark” is formed in an upper layer in each semiconductor chip region. The overlapping state of the alignment marks in the two layers gives the degree of overlay error. This method has been typically used in the automatic overlay measuring technique.
FIGS. 1A
to
1
F show a conventional fabrication method of a DRAM using the first conventional measuring method with the “alignment vernier caliper”.
First, as shown in
FIG. 1A
, a field oxide layer
102
is selectively formed on a main surface of a silicon substrate
101
by a selective oxidation process or the like, defining active regions. For the sake of simplification of description, only one of the active regions is shown in
FIGS. 1A
to
1
F, in which a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is formed.
Then, a gate oxide layer
104
a
is selectively formed on the exposed surface of the substrate
101
in the active region. Gate electrodes
103
are formed on the gate oxide layer
104
a
in the active region. Source/drain regions (not shown) are formed in the active region. Thus, two MOSFETs are adjacently formed in the active region, which serve as transfer transistors of the memory cell. These steps are performed by known processes.
Further, a silicon dioxide (SiO
2
) layer with a thickness of approximately 800 nm is formed on the whole substrate
101
to cover the MOSFETs by a Chemical Vapor Deposition (CVD) process, or the like. The bottom of the SiO
2
layer is contacted with the exposed area of the substrate
104
. The surface of the SiO
2
layer is then planarized by a Chemical-Mechanical Polishing (OMP) process. Thus, an interlayer insulating layer
104
made of SiO
2
is formed on the substrate
101
.
The interlayer insulating layer
104
may be formed by a Boron-doped Phosphorsilicate Glass (BPSG) layer whose surface is planarized by a reflow or etch-back process.
A patterned resist mask
105
is formed on the interlayer insulating layer
104
. This mask
105
has two square openings
105
A for forming contact holes
106
of the source/drain regions and three rectangular openings
105
Ba,
105
Bb, and
105
Bc for forming rectangular recesses
107
,
108
, and
109
serving as a lower alignment mark. The state at this stage is shown in FIG.
1
A.
Using the mask
105
, the interlayer insulating layer
104
and the gate oxide layer
104
a
are selectively removed by an anisotropically dry etching process, thereby forming the square contact holes
106
and the rectangular recesses
107
,
108
, and
109
. The contact holes
106
are located at the corresponding positions to the openings
105
A, respectively. The recesses
107
,
108
, and
109
are located at the corresponding positions to the openings
105
Ba,
105
Bb, and
105
Bc, respectively. The size or width of the contact holes
106
is smaller than that of the recesses
107
,
108
, and
109
. The state at this stage is shown in FIG.
1
B.
Subsequently, to fill the contact holes
106
, a polysilicon layer
110
with a thickness of 200 nm is deposited on the patterned interlayer insulating layer
104
, as shown in FIG.
1
C. Each of the contact holes
106
is entirely filled with the polysilicon layer
110
. However, since the size (or width) of the recesses
107
,
108
, and
109
is smaller than that of the contact holes
106
, the recesses
107
,
108
, and
109
are not filled with the polysilicon layer
110
. The layer
110
covers the side walls of the recesses
107
,
108
, and
109
and the exposed surface of the substrate
101
. Voids are generated in the respective recesses
107
,
108
, and
109
. The state at this stage is shown in FIG.
1
C.
The polysilicon layer
110
thus deposited is then etched back by a dry etching process until the surface of the interlayer insulating layer
104
is exposed. Thus, the polysilicon layer
110
existing in the contact holes
106
is selectively left, thereby forming polysilicon plugs
111
. At the same time, the polysilicon layer
110
existing in the recesses
107
,
108
, and
109
is selectively left, thereby forming polysilicon sidewalls
112
. The state at this stage is shown in FIG.
1
D.
Further, to form the lower electrodes of the storage capacitors for the MOSFETs, a polysilicon layer
113
with a thickness of approximately 800 nm is deposited on the interlayer insulating layer
104
over the entire substrate
101
by a CVD process. The state at this stage is shown in FIG.
1
E.
Depressions are generated in the surface of the polysilicon layer
113
due to the underlying recesses
107
,
108
, and
109
.
To pattern the polysilicon layer
113
thus deposited, a photoresist layer is uniformly formed on the layer
113
. Then, to pattern the polysilicon layer
113
, the layer
113
is subjected to reduction projection exposure and development processes. The photoresist layer thus patterned has square patterns
114
for forming the lower electrodes, and rectangular patterns
115
,
116
, and
117
for serving as an upper alignment mark. The state at this stage is shown in FIG.
1
F.
The patterns
115
,
116
, and
117
are located in the depression of the polysilicon layer
113
right over the corresponding recesses
107
,
108
, and
109
, respectively.
The rectangular recesses
107
,
108
, and
109
in the interlayer insulating layer
104
serve as the lower alignment mark. In other words, these recesses
107
,
108
, and
109
serve as a main scale of the alignment vernier caliper. The overlying rectangular patterns
115
,
116
, and
117
serve as the upper alignment mark. In other words, these patterns
115
,
116
, and
117
serve as a vernier scale of the alignment vernier caliper.
The overlay accuracy of the photoresist patterns
114
is determined or estimated by reading the overlapping state of the patterns
115
,
116
, and
117
with the corresponding recesses
107
,
108
, and
109
with the use of an optical microscope. Specifically, t
Guerrero Maria
Hayes Soloway Hennessey Grossman & Hage PC
Jr. Carl Whitehead
NEC Corporation
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