Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2007-10-09
2007-10-09
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C257S021000
Reexamination Certificate
active
10980232
ABSTRACT:
A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate11.The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
REFERENCES:
patent: 6207591 (2001-03-01), Aoki et al.
patent: 6770519 (2004-08-01), Ito et al.
patent: 2004/0018702 (2004-01-01), Ito et al.
patent: 02-294027 (1990-12-01), None
patent: 03-068134 (1991-03-01), None
patent: 08-148677 (1996-06-01), None
patent: 2000-260710 (2000-09-01), None
patent: 2002-151428 (2002-05-01), None
patent: 2002-359192 (2002-12-01), None
patent: 2003-197631 (2003-07-01), None
patent: 2003-528462 (2003-09-01), None
patent: 2003-309079 (2003-10-01), None
patent: 2005-019515 (2005-01-01), None
Notice of First Action mailed on Jan. 30, 2007, in counterpart Japanese Application No. 2003-376940.
Itani Takaharu
Ito Takayuki
Suguro Kyoichi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Geyer Scott B.
Ullah Elias
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