Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Utility Patent
1998-07-13
2001-01-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S588000
Utility Patent
active
06169018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device having dual gates, and more particularly to a fabrication method for dual gates which have gate insulating films having a different thickness.
2. Discussion of the background
FIGS. 1A
to
1
D are vertical cross-sectional diagrams illustrating a fabrication method for dual gates of a conventional semiconductor device.
First, in
FIG. 1A
, a first insulating film
12
, an oxide film, and a first poly silicon layer
13
are sequentially formed on a semiconductor substrate
11
, and a predetermined portion of the first insulating film
12
and the first poly silicon layer
13
, in which a second gate insulating film
14
a
is to be formed is removed.
In
FIG. 1B
, a second insulating film
14
which is an oxide film and a second poly silicon layer
15
are sequentially formed on the first poly silicon film
13
and the semiconductor substrate
11
. Here, the first insulating film
12
and the second insulating film
14
have a different thickness.
In
FIG. 1C
, a portion of the second insulating film
14
and the second poly silicon layer
15
, which is above the first poly silicon layer
13
is removed, and, as shown in
FIG. 1D
, by performing a gate patterning process there are formed a first gate insulating film
12
a
formed of the first insulating film
12
, a first gate electrode
13
a
of the first poly silicon film
13
, a second gate insulating film
14
a
of the second insulating film
14
, and a second gate electrode
15
a
of the second poly silicon layer
15
. Here, the first gate insulating film
12
a
and the second gate insulating film
14
a
have a different thickness.
According to the conventional fabrication method for the dual gates of the semiconductor device, when forming the second insulating film
14
, a portion of the second insulating film
14
, the oxide film, formed on the first poly silicon layer
13
is formed thicker than the other portion thereof formed on the semiconductor substrate
11
. Accordingly, a surface of the semiconductor substrate
11
beneath the first insulating film
12
has a tendency to be damaged while removing the portion of the second insulating film
14
formed on the first poly silicon layer
13
. In addition, when forming the second insulating film
14
, the first-formed poly silicon layer
13
passes through a high temperature condition, thus a grain size of the first poly silicon layer
13
becomes extremely enlarged so that an additional silicon ion implantation process is required.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a fabrication method for a semiconductor device that obviates the problem due to the related art.
An object of the present invention is to provide a fabrication method for a semiconductor device that improves reliability of a semiconductor device having dual gates and simplifies a manufacturing process thereof.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a fabrication method for a semiconductor device includes the steps of: providing a semiconductor substrate having a first region and a second region; sequentially forming a first insulating film and an oxidizable film on the first region of the substrate; forming a second insulating film on the second region of the substrate; forming a conductive layer on the second insulating film and the oxidizable film; and patterning the first insulating film, second insulating film, oxidizable film and conductive layer, for thereby forming a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode.
In the invention, when forming the second insulating film, the oxidizable film becomes an oxide film, which oxide film is combined with the first insulating film, for thereby forming the first gate insulating film.
The conductive layer is formed of either a multi-crystalline silicon or an amorphous silicon.
The insulating film is formed of either an oxide film, an oxide-nitride film, or a combination film of the oxide film and the oxide-nitride film, and a thickness thereof is about 10-100 Å.
The oxidizable film is formed of either a multi-crystalline silicon or an amorphous silicon, and a thickness thereof is about 10-100 Å.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide and further explanation of the invention as claimed.
REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5960289 (1999-10-01), Tsui et al.
Hoang Quoc
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Nelms David
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