Measuring and testing – Sampler – sample handling – etc.
Reexamination Certificate
2002-06-24
2004-12-07
Williams, Hezron (Department: 2856)
Measuring and testing
Sampler, sample handling, etc.
C250S304000, C438S014000, C438S017000
Reexamination Certificate
active
06826971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a sample to be analyzed, in particular, a fabrication method for a sample to be analyzed wherein a sample for examining defective portions of a semiconductor device is fabricated.
2. Description of the Background Art
In the case that a defect occurs during the course of the manufacturing process of a semiconductor device or in the case that a defect occurs in a semiconductor device that is on the market, a defect analysis is carried out in order to determine the cause of that defect.
A fabrication method of a sample using a microsampling method and the structure of this sample shown as a fabrication method of a sample for a physical analysis used in a defect analysis by using a transmission electron microscope (hereinafter referred to as “TEM”), or the like, in, for example, Reference 1 (Japanese Patent Laying-Open No. 5-52721), Reference 2 (Japanese Patent Laying-open No. 11-258130), Reference 3 (Japanese Patent Laying-Open No. 11-108813) and Reference 4 (T. Ohnishi et al., “A New Focused-Ion-Beam Microsampling Technique for TEM Observation of Site-specific Area's”, Proc. 25th Int. Symp. for Testing and Failure Analysis (1999) p. 449).
In addition, a fabrication method of a sample using a pick up method and the structure of this sample are shown as a fabrication method of a sample for a physical analysis that is used for a defect analysis in Reference 5 (R. J. Young et al., “High-Yield and High-Throughput TEM Sample Preparation Using Focused Ion Beam Automation”, Proc. 24th Int. Symp. for Testing and Failure Analysis (1998) p. 329).
Furthermore, a technique for carrying out a defect analysis by means of a scanning electron microscope (hereinafter referred to as “SEM”), or the like, from the rear surface of a silicon device that is exposed by removing the silicon substrate in the device through etching is disclosed in Reference 6 (P. Malberti et al., “A new Back-Etch for Silicon Devices”, Proc. 21st Int. Symp. for Testing and Failure Analysis (1995) p. 257) and in Reference 7 (D. Corum et al., “Practical Applications of Backside Silicon Etching”, Proc. 21st Int. Symp. for Testing and Failure Analysis (1995) p. 263).
However, the following problems arise in the above described conventional fabrication method of a sample for defect analysis. A sample is extracted from the surface of a semiconductor device so as to include a defective portion according to the methods shown in Reference 1 to Reference 5, respectively. A multi-layered wire structure is adopted in many semiconductor devices.
Therefore, in the case that a defective portion, such as a foreign substance or a flaw, existing in the vicinity of the surface of a silicon substrate must be selectively examined, the targeted defective portion must be exposed by removing wires, layer by layer, from the wires located on the top layer in order to become visible to a SEM or to a scanning ion microscope (hereinafter referred to as “SIM”).
In order to remove the wires, it becomes necessary to establish, in advance, the conditions for removal of the wires, such as the calculation of the period of etching time from the etching rate of the etchant for the wires. In addition, it takes time for the removal, itself, of the wires.
Therefore, there is a problem that a great amount of time and labor must be spent before the defective portion can be observed.
In addition, according to techniques shown in Reference 6 and Reference 7, respectively, observation can only be carried out from the rear surface of a semiconductor device. Therefore, there is a problem that information concerning the detailed structure, composition, or the like, of the defective portion, such as the three dimensional structure of the defective portion, cannot be gained.
SUMMARY OF THE INVENTION
The present invention is provided in order to solve the above described problems and the purpose thereof is to provide a fabrication method of a sample to be analyzed wherein a sample with a defective portion located, in particular, in the vicinity of the surface of a semiconductor substrate from among the defective portions that have occurred in a semiconductor device is fabricated so that detailed information of this portion can be gained.
A fabrication method of a sample to be analyzed according to one aspect of the present invention is a fabrication method of a sample to be analyzed wherein a sample is fabricated for analyzing a defect that has occurred in a semiconductor device that includes a semiconductor substrate and an element formation portion formed on this semiconductor substrate and is provided with the following steps. The semiconductor substrate is removed so as to expose the surface, which faces the substrate, that contacts the semiconductor substrate in the element formation portion. A sample body is extracted from the surface, which faces the substrate, that is exposed so that the cross section of the element formation portion is exposed. The surface of the extracted sample body on the side opposite to the surface facing the substrate is secured to a sample supporting portion and, thereby, the sample body is set on the sample supporting portion.
According to this fabrication method of a sample to be analyzed, the surface, which faces the substrate, that contacts the semiconductor substrate in the element formation portion is exposed and the cross section of the element formation portion is also exposed and, thereby, a defective portion located in the vicinity of the surface of the semiconductor substrate, in particular, can be easily observed and evaluated without sequentially removing a plurality of wires located in the upper layers.
In addition, it is preferable to provide the step of forming a protective film on the surface, which faces the substrate, that has been exposed between the step of exposing the surface facing the substrate and the step of extracting the sample body.
In this case, at the time of the detachment of the sample body by means of a focused ion beam, the detachment can be carried out without damaging the exposed surface facing the substrate.
Furthermore, one example of a preferable sample supporting portion that can be used in the step of concretely setting the sample body onto the sample supporting portion is a supporting portion of a mesh form.
Here, in the step of the extraction of the sample body, it is preferable for the sample body to be extracted to be of an order of size of microns and, thereby, a sample that includes a defective portion can be easily handled and can be analyzed in a comparatively easy manner.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4939364 (1990-07-01), Ishitani et al.
patent: 6281025 (2001-08-01), Ring et al.
patent: 6303399 (2001-10-01), Engelmann et al.
patent: 6420722 (2002-07-01), Moore et al.
patent: 2002/0024011 (2002-02-01), Shimizu
patent: 2002/0050565 (2002-05-01), Tokuda et al.
patent: 5-52721 (1993-03-01), None
patent: 11-108813 (1999-04-01), None
patent: 11-258130 (1999-09-01), None
T. Ohnishi, et al, “A New Focused-Ion-Bean Microsampling Technique for TEM Observation of Site-Specific Area's” Proceedings from the 25th International Symposium for Testing and Failure Analysis, Nov. 14-18, 1999, pp. 449-453.
R. J. Young, et al, “High-Yield and High-Throughput TEM Sample Preparation Using Focused Ion Bean Automation” Proceedings from the 24th International Symposium for Testing and Failure Analysis, Nov. 15-19, 1998, pp. 329-336.
P. Malberti, et al, “A New Back-Etch For Silicon Devices” Proceedings from the 21st International Symposium for Testing and Failure Analysis, Nov. 6-10, 1995, pp. 257-261.
D. Corum, et al, “Practical Applications of Backside Silicon Etching” Proceedings from the 21st International Symposium for Testing and Failure Analysis, Nov. 6-10, 199
Fayyaz Nashmiya
Renesas Technology Corp.
Williams Hezron
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