Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-28
2004-04-13
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S321000
Reexamination Certificate
active
06720611
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a fabrication method for a flash memory, and more particularly relates to a fabrication method for a self-aligned flash memory.
BACKGROUND OF THE INVENTION
A computer with advanced function must process a large amount of data, which requires more memory. At the end of 1980, Intel developed the “flash memory” which is based on the same framework as electrically erasable programmable read only memory, EEPROM. Because of the number of times of data is stored, read and erased is not limited, and the flash memory has become the fastest memory developed.
Nonvolatile memory, especially flash memory, is becoming more and more important in many applications. In recent years, the demand for flash memory has exceeded that for other kinds of memory. Therefore, how to develop the new generation of technology and how to reduce the area of flash memory are the challenges facing engineers.
The framework of the flash memory is similar to that of the EPROM, having a stacked gate structure comprising a control gate and a floating gate. The only difference is the thin and high quality tunnel silicon oxide layer under the floating gate. When the program is written into the flash memory, the hot carrier tunnels through the thin tunnel silicon oxide layer to the floating gate, which is similar in operational method to the EPROM. When erasing the program, a negative voltage is applied to the control gate to force the carrier trapped in the floating gate to tunnel through the thin tunnel silicon oxide layer to the source area.
Although flash memory and the EEPROM have the same framework, the erasing method is different. The volume of the flash memory is much smaller than that of the EEPROM. Moreover, the time required to erase data is about one to two seconds. This is much faster than EPROM, which requires twenty minutes and ultraviolet (UV) rays as the source to erase the data. Therefore, the flash memory has advantages over EPROM and EEPROM.
FIG. 1
illustrates a flash memory fabricated by the conventional method. It comprises using a photomask (not shown in the figure) to define the active area
16
on the P-type substrate
10
. Next, a dry etching is performed to create a recess in the wafer for formation of shallow trench isolation
17
(STI), the depth thereof being about 200 to 400 nm in the substrate
10
. Then the photomask is removed and a stacked gate structure is formed over the substrate
10
. The stacked gate structure includes a tunnel silicon oxide layer
12
and a floating gate
13
. Next, an ONO (oxide
itride/oxide) insulating layer
14
and control gate layer
15
are sequentially formed over the tunnel silicon oxide layer
12
and a floating gate
13
. It is noted that additional photomask is required to define the area of the floating gate
13
. Therefore, at least two different kinds of photomasks are required to form the floating gate
13
and active area
16
in the conventional method.
It is assumed that a V voltage is applied to the control gate layer
15
and a zero voltage is applied to the substrate
10
. Because the substrate
10
, the floating gate layer
13
and the control gate layer
15
present the capacitance coupling state, the floating gate voltage (V
FG
) is determined according to the following formula:
V
FG
=
V
×
C
2
C
1
+
C
2
C
1
is the capacitance between the substrate
10
and the floating gate
13
. C
2
is the capacitance between the floating gate
13
and the control gate layer
15
.
When the channel length is reduced to 0.18 &mgr;m, even to 0.13 &mgr;m, the conventional non-using self aligned fabrication technology of flash memory experiences misalignment between the floating gate layer
13
and active area
16
. On the other hand, this kind of flash memory that injects a carrier into the floating gate layer to store data has a faster injection velocity if the tunnel silicon oxide layer
12
is thinner or the floating gate layer
13
covers more of the source area. However, the thinner tunnel silicon oxide layer
12
also reduces the data retention time.
On the other hand, under constant applied voltage, the voltage V
FG
of the floating gate layer
13
can be increased by increasing the capacitance of C2 such that the applied voltage can be coupled more to the floating gate layer
13
. That is, the area between the floating gate layer
13
and the control gate layer
15
is increased. The foregoing method can lower the applied voltage to generate the tunnel current of tunnel silicon oxide layer
12
. However, because of the limit of photolithography process, the isolation distance between the floating gates is also limited. Therefore, a greater area of shallow trench isolation
17
is necessary because of the limit of photolithography process when using the method of increasing the covering area to increase the capacitance of C2. This, in turn, increases the area of the flash memory. A conventional method of using the spacer process to overcome the foregoing drawback also requires a photolithography process so that the whole reduced area of flash memory is still limited.
Therefore, resolution of the misalignment problem between the floating gate
13
and active area
16
and how to increase the capacitance of C2 but not increase the whole area of flash memory is the greatest challenge facing engineers today.
SUMMARY OF THE INVENTION
In accordance with the forgoing description, two photo masks are respectively required to form the floating gate layer and the active area of the conventional method. Precise control is very difficult to attain during the alignment process. Therefore, one of the purposes of the present invention is to provide a self-aligned process for flash memory to resolve the misalignment problem.
Another purpose of the present invention is to provide a new kind of floating gate structure and a related process method. The method may increase the coupling area between the floating gate layer and the control gate layer to raise the coupling capacitance thereof but not increase the whole area of the flash memory.
The process method of the present invention comprises these steps. Firstly, a shallow trench isolation is formed on a semiconductor wafer to form the active area islands. Next, the shallow trench isolation is etched to form an indented shallow trench isolation which forms the active area islands. A silicon oxide layer is formed over the indented shallow trench isolation and the surface of the wafer. An anisotropic dry etching step is performed on the silicon oxide layer to form dielectric spacers surrounding the sides of the active area. Then, a thermal process is performed to form a thin tunnel silicon oxide layer. A doped polysilicon layer is deposited as a floating gate over the tunnel silicon oxide layer, dielectric spacers and indented shallow trench isolation. Next, the indented shallow trench isolation between the active area islands is filled with a silicon nitride layer. Then, a thermal oxide layer is grown on the polysilicon layer not covered by the silicon nitride layer. Hot phosphoric acid is used to remove the silicon nitride layer. Using the thermal oxide layer as a mask, the polysilicon layer is etched to isolate the floating gate. Next, a dielectric layer comprising oxide-nitride-oxide (O/N/O) is sequentially deposited on the surface. A doped polysilicon gate is formed as a control gate over the dielectric layer. Then, conventional photolithography and etching processes are performed on the gate structure to form the word line. Finally, a source and drain area ion implant is performed, after which the self-aligned flash cell is complete.
Formation of a floating gate according to the present invention does not require a photolithography step so the method does not suffer misalignment between the floating gate and the active area. On the other hand, the active area islands are formed by etching the shallow trench isolation. Therefore, the coupling area between the floating gate layer and the control gate layer may be increased by raising the etching dep
Dickinson Wright PLLC
Nguyen Tuan H.
Winbond Electronics Corporation
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