Fabrication method for electronic system modules

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Reexamination Certificate

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07615478

ABSTRACT:
This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

REFERENCES:
patent: 4672421 (1987-06-01), Lin
patent: 4767189 (1988-08-01), Hayashi et al.
patent: 4862322 (1989-08-01), Bickford et al.
patent: 5024372 (1991-06-01), Altman et al.
patent: 5074947 (1991-12-01), Estes et al.
patent: 5103290 (1992-04-01), Temple et al.
patent: 5214250 (1993-05-01), Cayson et al.
patent: 5267867 (1993-12-01), Agahdel et al.
patent: 5290970 (1994-03-01), Currie
patent: 5367593 (1994-11-01), Lebby et al.
patent: 5382545 (1995-01-01), Hong
patent: 5404175 (1995-04-01), Nagae et al.
patent: 5534465 (1996-07-01), Frye et al.
patent: 5534466 (1996-07-01), Perfecto et al.
patent: 5550083 (1996-08-01), Koide et al.
patent: 5579574 (1996-12-01), Colleran et al.
patent: 5627406 (1997-05-01), Pace
patent: 5700737 (1997-12-01), Yu et al.
patent: 5841193 (1998-11-01), Eichelberger
patent: 5912510 (1999-06-01), Hwang et al.
patent: 5918364 (1999-07-01), Kulesza et al.
patent: 5972152 (1999-10-01), Lake et al.
patent: 5998738 (1999-12-01), Li et al.
patent: 6103554 (2000-08-01), Son et al.
patent: 6138348 (2000-10-01), Kulesza et al.
patent: 6141245 (2000-10-01), Bertin et al.
patent: 6174804 (2001-01-01), Hsu
patent: 6175161 (2001-01-01), Goetz et al.
patent: 6180687 (2001-01-01), Hammer et al.
patent: 6180867 (2001-01-01), Hedengren et al.
patent: 6246010 (2001-06-01), Zenner et al.
patent: 6329610 (2001-12-01), Takubo et al.
patent: 6372549 (2002-04-01), Urushima
patent: 6515870 (2003-02-01), Skinner et al.
patent: 6528891 (2003-03-01), Lin
patent: 6664176 (2003-12-01), Hedler et al.
patent: 6846737 (2005-01-01), Towle et al.
patent: 6881609 (2005-04-01), Salmon
patent: 6927471 (2005-08-01), Salmon
patent: 7297572 (2007-11-01), Salmon
patent: 2001/0020549 (2001-09-01), Horiuchi et al.
patent: 2001/0026010 (2001-10-01), Horiuchi et al.
patent: 2001/0046586 (2001-11-01), Chan et al.
patent: 2002/0151164 (2002-10-01), Jiang et al.
patent: 1089331 (2001-04-01), None
patent: 07169873 (1995-07-01), None
patent: WO 91/09419 (1991-06-01), None
patent: WO 92/07378 (1992-04-01), None
patent: WO 95/05675 (1995-02-01), None
Davis et al., “Thin Film Metallization of Three Dimensional Substrates,” May 1-4, 1994, Electronic Components Technology Conference, Proceedings 44th, pp. 359-361.
U.S. Appl. No. 10/237,640, filed Sep. 6, 2002, now Patent No. 6,627,471, Office Action mailed Oct. 5, 2004.
U.S. Appl. No. 10/237,640, filed Sep. 6, 2002, now Patent No. 6,627,471, Applicant Response to Office Action received by the USPTO on Jan. 24, 2005.
U.S. Appl. No. 10/237,640, filed Sep. 6, 2002, now Patent No. 6,627,471, Notice of Allowance mailed Apr. 15, 2005.
U.S. Appl. No. 10/701,888, filed Nov. 4, 2003, now Patent No. 6,881,609, Office Action mailed May 21, 2004.
U.S. Appl. No. 10/701,888, filed Nov. 4, 2003, now Patent No. 6,881,609, Applicant Response to Office Action received by the USPTO on Aug. 30, 2004.
U.S. Appl. No. 10/701,888, filed Nov. 4, 2003, now Patent No. 6,881,609, Notice of Allowance mailed Dec. 9, 2004.
U.S. Appl. No. 10/702,235, filed Nov. 5, 2003, Restriction Requirement mailed Jun. 28, 2005.
U.S. Appl. No. 10/702,235, filed Nov. 5, 2003, Applicant Response to Restriction Requirement received by the USPTO on Aug. 5, 2005.
U.S. Appl. No. 10/702,235, filed Nov. 5, 2003, Office Action mailed Oct. 3, 2005.
U.S. Appl. No. 10/702,235, filed Nov. 5, 2003, Applicant Response to Office Action received by the USPTO on Apr. 7, 2006.
U.S. Appl. No. 10/702,235, filed Nov. 05, 2003, Office Action mailed Dec. 15, 2006.
U.S. Appl. No. 10/702,235, filed Nov. 5, 2003, Applicant Response to Office Action received by the USPTO on Jun. 15, 2007.
U.S. Appl. No. 11/066,964, filed Feb. 25, 2005, Restriction Requirement mailed Jun. 5, 2007.
U.S. Appl. No. 11/066,964, filed Feb. 25, 2005, Applicant Response to Office Action received by the USPTO on Jul. 16, 2007.
U.S. Appl. No. 11/066,964, filed Feb. 25, 2005, Office Action mailed Jul. 8, 2008.
Notice of Allowance For U.S. Appl. No. 10/702,235 Mailed Jul. 24, 2007.
Restriction Requirement Mailed Mar. 30, 2006 For U.S. Appl. No. 11/066,964.
Response to Restriction Requirement Received by the USPTO on Apr. 17, 2006 For U.S. Appl. No. 11/066,964.
Restriction Requirement Mailed Jun. 30, 2006 For U.S. Appl. No. 11/066,964.
Response to Restriction Requirement Received by the USPTO on Nov. 2, 2006 For U.S. Appl. No. 11/066,964.
Notice of Non-Complaint Amendment Mailed Jan. 30, 2007 For U.S. Appl. No. 11/066,964.
Response to Notice of Non-Complaint Amendment Received by the USPTO on Mar. 9, 2007 For U.S. Appl. No. 11/066,964.
Non-Final Office Action For U.S. Appl. No. 11/066,964 Mailed Oct. 9, 2007.
Response to Office Action Received by the USPTO on Mar. 28, 2008 For U.S. Appl. No. 11/066,964.
Response to Final Office Action Received by the USPTO on Sep. 18, 2008 For U.S. Appl. No. 11/066,964.
Requirement for Restriction/Election for U.S. Appl. No. 10/237,640, mailed Jun. 15, 2004, 5 pages.
Response to Requirement for Restriction/Election for U.S. Appl. No. 10/237,640, Received by the USPTO on Jul. 12, 2004, 2 pages.
Non-Final Office Action for U.S. Appl. No. 11/066,964, mailed Oct. 30, 2008, 5 pages.
Requirement for Restriction/Election for U.S. Appl. No. 11/868,912, mailed Mar. 13, 2009, 7 pages.
Response to Requirement for Restriction/Election for U.S. Appl. No. 11/868,912, mailed Apr. 10, 2009, 8 pages.
Non-Final Office Action for U.S. Appl. No. 11/868,912 Mailed Jun. 18, 2009, 16 pages.
Non-Final Office Action for U.S. Appl. No. 11/868,919 Mailed Apr. 28, 2009, 32 pages.

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