Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-11-20
2007-11-20
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
10702235
ABSTRACT:
This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.
REFERENCES:
patent: 4862322 (1989-08-01), Bickford et al.
patent: 5074947 (1991-12-01), Estes et al.
patent: 5214250 (1993-05-01), Cayson et al.
patent: 5267867 (1993-12-01), Agahdel et al.
patent: 5290970 (1994-03-01), Currie
patent: 5367593 (1994-11-01), Lebby et al.
patent: 5382545 (1995-01-01), Hong
patent: 5579574 (1996-12-01), Colleran et al.
patent: 5627406 (1997-05-01), Pace
patent: 5700737 (1997-12-01), Yu et al.
patent: 5841193 (1998-11-01), Eichelberger
patent: 5918364 (1999-07-01), Kulesza et al.
patent: 5972152 (1999-10-01), Lake et al.
patent: 5998738 (1999-12-01), Li et al.
patent: 6103554 (2000-08-01), Son et al.
patent: 6138348 (2000-10-01), Kulesza et al.
patent: 6141245 (2000-10-01), Bertin et al.
patent: 6174804 (2001-01-01), Hsu
patent: 6246010 (2001-06-01), Zenner et al.
patent: 6372549 (2002-04-01), Urushima
patent: 6515870 (2003-02-01), Skinner et al.
patent: 6528891 (2003-03-01), Lin
patent: 6664176 (2003-12-01), Hedler et al.
patent: 6846737 (2005-01-01), Towle et al.
patent: 1089331 (2001-04-01), None
patent: 07169873 (1995-07-01), None
patent: WO 91/09419 (1991-06-01), None
patent: WO 92/07378 (1992-04-01), None
patent: WO 95/05675 (1995-02-01), None
J. Lynn Davis and J. Kevin Arledge, “Thin Film Metallization of Three Dimensional Substrates,” May 1-4, 1994, Electronic Components Technology Conference, Proceedings 44th, pp. 359-361.
U.S. Appl. No. 11/066,964, filed Feb. 25, 2005, Restriction Requirement mailed Jun. 05, 2007.
U.S. Appl. No. 11/066,964, filed Feb. 25, 2005, Applicant Response to Office Action received by the USPTO on Jul. 16, 2007.
Harrison Monica D.
Hynix / Semiconductor Inc.
Jr. Carl Whitehead
Townsend and Townsend / and Crew LLP
LandOfFree
Fabrication method for electronic system modules does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication method for electronic system modules, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for electronic system modules will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3880142