Fabrication method for an insulation structure having a low diel

Details Fabrication method for an insulation structure having a low diel Fabrication method for an insulation structure having a low diel

1999-07-23

2000-07-18

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438623, 438624, 438639, H01L 214763

Patent

active

060906987

ABSTRACT:
A low-dielectric constant insulation structure is described in which low-dielectric constant insulation layers and silicon oxide layers are alternately stacked on the substrate to form a stacked insulation layer. A required pattern is then etched in the stacked insulation layer followed by a selective etching to remove a portion of the low dielectric insulation layer to form, starting from the sidewall of the stacked insulation layer and extending inwardly, a plurality of recessed regions. A sputtering deposition and etching-back are further conducted on the sidewall of the stacked insulation layer to form a sidewall spacer to enclose the already formed recessed regions. A plurality of air-gaps is formed in the stacked insulation layer to establish a low dielectric insulation structure.

REFERENCES:
patent: 5252517 (1993-10-01), Blalock et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5616960 (1997-04-01), Noda et al.
patent: 5953625 (1999-09-01), Bang

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