Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-18
2004-08-24
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S626000, C438S633000, C438S926000
Reexamination Certificate
active
06782512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. In particular, it relates to a method of deciding whether to add a dummy pattern to a conductive pattern such as a metal wiring pattern formed on a semiconductor substrate, in order to planarize a dielectric layer covering the conductive pattern.
2. Description of the Related Art
The deposition of a layer of dielectric material to cover a conductive pattern on a semiconductor substrate is a common step in the fabrication of semiconductor devices. This step is often carried out by chemical vapor deposition (CVD).
In a semiconductor device having a multilayer wiring structure, another conductive pattern is formed on the dielectric layer as an upper wiring layer. Before this conductive pattern is formed, the surface of the dielectric layer is planarized by, for example, chemical-mechanical polishing (CMP). CMP produces a flat surface provided the conductive pattern buried within the dielectric layer has a substantially even density.
It is not easy, however, to design a semiconductor device so that the conductive pattern formed on the substrate has an even density, and if density differences exist, the surface of the polished dielectric layer will show global height differences between areas of high pattern density and areas of low pattern density. These global height differences lead to reduced precision when photolithography is used to form the upper wiring layer on the dielectric layer.
A known way to reduce global height differences is to add dummy patterns to the low-density areas, to increase the pattern density in these areas. Conventionally, the circuit designer uses visual estimation to decide where to place dummy patterns.
Estimating by eye where it is necessary to place dummy patterns, however, is a method that depends greatly on the designer's judgment. It may happen, for example, that although the actual density of the conductive pattern in a certain area is comparatively high, the designer perceives the density as low and decides to add a dummy pattern to the area. The pattern density in the area is then further increased, and in the device as a whole, global height differences are aggravated instead of being reduced.
In addition, each designer's judgment differs, and no two designers will decide to form dummy patterns in the same places, so a suitable reduction of global height differences is difficult to achieve.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of deciding where to form dummy patterns that can effectively reduce global height differences, thereby enabling semiconductor devices to be fabricated with higher precision than before.
The present invention provides a method of fabricating a semiconductor device in which a conductive pattern formed on a semiconductor substrate is covered by a dielectric layer, and a dummy pattern is added to the conductive pattern so that the dielectric layer can be more flatly planarized. To decide whether to form a dummy pattern in a given region on the semiconductor substrate, the proportion of a prescribed region, including the given region, that is covered by the conductive pattern is calculated, and the decision is based on the calculated proportion (the conductive pattern density). After the conductive pattern and dummy pattern have been formed, the dielectric layer is deposited and planarized by chemical-mechanical polishing. The conductive pattern typically projects above the semiconductor substrate and is electrically connected to circuit elements formed in the semiconductor substrate, while the dummy pattern, which also projects above the semiconductor substrate, is electrically disconnected from the circuit elements.
According to the invented method, the dummy pattern is formed according to a fixed rule, without relying on a designer's judgment. For example, the proportion of the prescribed region covered by conductive pattern may be compared with a predetermined threshold, a dummy pattern being added if the density is equal to or less than the threshold value. Since a fixed rule is followed, an appropriate combined pattern density is consistently obtained, so that when the dielectric layer is planarized, global height differences are consistently reduced.
The semiconductor substrate may be one part of a semiconductor wafer, and may be partitioned into square or rectangular sections, the given region being one of the square or rectangular sections and the prescribed region comprising one or more of the square or rectangular sections. If composed of two or more of the square or rectangular sections, the prescribed region itself may have a square or rectangular shape.
The decision as to whether to form the dummy pattern may be based on an adjusted proportion different from the actual proportion of the prescribed region covered by the conductive pattern. The adjustment may be made to allow for a difference between the area of the conductive pattern and the area of the raised portions of the dielectric layer formed above the conductive pattern. For example, if a parallel-plate type of plasma CVD apparatus is used to deposit the dielectric layer, the raised portions of the dielectric layer are larger than the conductive pattern; the adjusted proportion then preferably exceeds the actual proportion. If a high-density plasma CVD apparatus is used, the raised portions of the dielectric layer are smaller than the conductive pattern, and the adjusted proportion is preferably less than the actual proportion.
The dimensions of the dummy pattern may be varied according to proportion of the prescribed region covered by the conductive pattern. For example, the dummy pattern dimensions may be increased as the proportion of the prescribed region covered by the conductive pattern decreases. In particular, the dimensions may be varied so that the sum of the dummy pattern density in the given region and the conductive pattern density in the prescribed region exceeds a predetermined threshold.
The present invention also provides a method of deciding whether to form a dummy pattern in a given region on a semiconductor substrate. The ratio of the area of the conductive pattern in the prescribed region to the area of a prescribed region including the given region is calculated, and the dummy pattern is formed if the ratio is less than a predetermined threshold. The calculated area of the conductive pattern may differ from the actual area.
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Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Whitmore Stacy A.
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