Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-07
2001-06-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S643000, C438S653000, C438S669000
Reexamination Certificate
active
06242342
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88113786, filed Aug. 12, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for an integrated circuit. More particularly, the present invention relates to a fabrication method for a via.
2. Description of the Related Art
The multilevels interconnect structure has been widely employed to accommodate the escalating demands of high densificiation and performance associated with the design of the continued downscaling of the device dimensions in the ultra large scale integration semiconductor devices. To electrically connect the various levels of different metal layers, the via plug technique has been developed
FIG. 1
is a schematic, cross-sectional view of an interconnect structure according to the prior art. The conventional methodology for forming an interconnect structure involves the formation of a dielectric layer
102
, which can either be an interlevel metal dielectric layer (ILD) or an interlevel metal dielectric layer (IMD), on a substrate
100
. A metal layer, such as aluminum or an aluminum alloy, is then deposited on the first dielectric layer
102
. The metal layer is further patterned to form a metal conductive feature such as a metal conductive line
104
. An interlevel metal dielectric layer (IMD), such as spin-on-glass (SOG), is then formed on the resulting metal conductive feature
104
. An opening
108
is further formed in the inner metal dielectric layer (IMD). A conductive material is formed filling the opening
108
to form a via plug
110
, where the entire bottom surface of the via plug
110
is in a direct contact with the metal conductive feature
104
.
Accompanying the increase of the integration of a semiconductor device, the density of the interconnect structures, as shown in
FIG. 1
, is also greatly increased. As a result, the borderless via technique, which provides a space saving advantage, gradually becomes the core technology for the fabrication of these types of interconnect structures. In a highly integrated device, however, the borderless via plug
110
is often not aligned with the underlying metal conductive feature
104
, resulting in an incomplete landing on the metal conductive feature
104
and extending off of the metal conductive feature onto the surrounding dielectric material. This type of misalignment critically affects the yield of the production, and a method to correctly stack the borderless via plug
110
on the metal conductive feature
104
is thereby therefore needed.
SUMMARY OF THE INVENTION
The current invention provides a fabrication method for a borderless landed via on a semiconductor device in which the via plug is aligned with the underlying metal conductive feature, such as a conductive line. According to the present invention, a substrate comprising a first dielectric layer is provided. A first conductive layer and a metal layer are sequentially formed on the first dielectric layer, and the metal layer is covered with a first patterned mask. The metal layer is then etched to form a metal plug using the first patterned mask as an etching mask. A second patterned mask is then formed on the substrate to pattern the metal conductive feature. Using the first patterned mask and the second patterned mask as etching masks, the conductive layer is etched to form a conductive line. The metal plug is thus aligned with and completely landed on the conductive line. Thereafter, a second dielectric layer is formed on the substrate, tightly enclosing the metal plug and the conductive line.
The metal layer includes tungsten, aluminum or copper. The conductive layer is, for example, metal or doped polysilicon. A barrier layer can also be formed between the conductive layer and the metal layer, which can be etched before the etching of the conductive layer. Furthermore, both the first mask pattern and the second mask pattern can be, for example, a photoresist material.
According to the present invention, the first photoresist pattern is used to form the via, and both the first and the second photoresist patterns are used to form and the conductive line. Since the via and the underlying conductive line formed subsequently are formed by using the first photoresist pattern, the via formed is thus aligned with the underlying conductive line and is completely landed on the underlying conductive line even if the first photoresist pattern may not be aligned with the second photoresist pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 4917759 (1990-04-01), Fisher et al.
patent: 4954423 (1990-09-01), McMann et al.
patent: 4960489 (1990-10-01), Roeska et al.
patent: 4966864 (1990-10-01), Pfiester
patent: 5132775 (1992-07-01), Brighton et al.
patent: 5175127 (1992-12-01), Manning
patent: 5436199 (1995-07-01), Brighton
patent: 5665642 (1997-09-01), Kato
Gurley Lynne
Huang Jiawei
J.C. Patents
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd.
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