Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-11-24
1999-12-07
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257298, 257370, 257401, H01L 2972
Patent
active
059988207
ABSTRACT:
A DRAM cell structure having charge amplification is disclosed. The DRAM cell has a capacitor to store an electrical charge. The DRAM cell further has a MOS transistor. The gate of the MOS transistor is coupled to a word line control to activate and deactivate the MOS transistor. The drain MOS transistor is coupled to one plate of the capacitor. The DRAM cell has a bipolar transistor to amplify the electrical charge stored on the capacitor. The bipolar transistor has a base that is the source for the MOS transistor. The base of the bipolar transistors is formed by masking and implanting a material of the first conductivity type adjacent to the gate to form the base. The collector of the bipolar transistor is the semiconductor substrate. The bipolar transistor has an emitter coupled to a bit-lines control which when activated will sense the charge amplified by the bipolar transistor. The emitter is formed by masking and implanting a material of the second conductivity type within the material of the first conductivity type. The emitter is implanted to ensure a large overlap of the gate of the emitter. The overlap of the gate of the emitter will ensure generation of gate induced drain leakage current to discharge the storage capacitor during writing of a logical "0" to the storage capacitor.
REFERENCES:
patent: 4677589 (1987-06-01), Haskell et al.
patent: 4791611 (1988-12-01), Eldin et al.
patent: 5066607 (1991-11-01), Banerjee
patent: 5363325 (1994-11-01), Sunouchi et al.
"The Evolution of DRAM Cell Technology" by B. El-Kareh et al. Solid State Technology, May 1997, pp. 89-101.
"A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Dram's " M. Terauchi et al, Digest of VLSI Technology Symposium, pp. 21-22.
"A Complentary Gain Cell Technology For Sub-1v Supply Drams" Shukuri et al, Digest of IEDM, pp. 1006-1992.
"Super-Low-Voltage Operation of Semi-Static Complementary Gain DRAM Memory Cell", Shukuri et al. Digest of VLSI Technology Sympsium, p. 23, 1993.
"A Novel Merged Gain Cell For Logic Compatible High Density Drams". M. Mukai et al, Digest of VLSI Technology Symposium, p. 155, 1997.
Ackerman Stephen B.
Knowles Billy J.
Saile George O.
Vanguard International Semiconductor Corporation
Wojciechowicz Edward
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