Fabrication and method of operation of multi-level memory...

Details Fabrication and method of operation of multi-level memory... Fabrication and method of operation of multi-level memory...

2011-03-29

2011-03-29

Dickey, Thomas L (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27103

Reexamination Certificate

active

07915663

ABSTRACT:
A semiconductor device includes an insulation layer (14) provided on a semiconductor substrate (12), a p-type semiconductor region (16) provided on the insulation layer, an isolation region (18) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region (20) and an n-type drain region (22) provided on the p-type semiconductor region, a charge storage region (30) provided above the p-type semiconductor region between the n-type source region and the n-type drain region, and an voltage applying portion that applies a different voltage to the p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being preformed.

REFERENCES:
patent: 5696718 (1997-12-01), Hartmann
patent: 5889302 (1999-03-01), Liu
patent: 1120045 (1989-05-01), None
patent: 7074241 (1995-03-01), None
patent: 8213573 (1996-08-01), None
patent: 9074146 (1997-03-01), None
patent: 2003318289 (2003-11-01), None

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