Fabricating vias of different size of a semiconductor device...

Details Fabricating vias of different size of a semiconductor device... Fabricating vias of different size of a semiconductor device...

2011-07-12

2011-07-12

Lee, Hsien-ming (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000, C438S672000, C257S774000, C257SE21577, C257SE21579, C257SE21585

Reexamination Certificate

active

07977237

ABSTRACT:
When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.

REFERENCES:
patent: 2009/0197422 (2009-08-01), Kang et al.

Affiliated with

Also associated with

Rating

Fabricating vias of different size of a semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabricating vias of different size of a semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabricating vias of different size of a semiconductor device... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2660774