Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-07-05
2002-10-15
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S052000, C438S739000
Reexamination Certificate
active
06465357
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the process of manufacturing structures on a silicon substrate. More specifically, the present invention relates to devices created through a process that uses chemically-selective endpoint detection to fabricate structures on a silicon substrate.
2. Related Art
The dramatic advances in computer system performance during the past 20 years can largely be attributed to improvements in the processes that are used to fabricate integrated circuits. By making use of the latest processes, integrated circuit designers can presently integrate computing systems comprised of hundreds of millions of transistors onto a single semiconductor die which is a fraction of the size of a human fingernail.
This integrated circuit fabrication technology is also being used to fabricate Micro-Electro-Mechanical Systems (MEMs), such as microscopic motors and other types of actuators, that are invisible to the unaided human eye, and which have dimensions measured in fractions of microns.
A typical fabrication process builds structures through successive cycles of layer deposition and subtractive processing, such as etching. As the dimensions of individual circuit elements (or MEMs structures) continues to decrease, it is becoming necessary to more tightly control the etching operation. For example, in a typical etching process, etching is performed for an amount of time that is estimated by taking into account the time to etch through a layer to reach an underlying layer, and the time to overetch into the underlying layer. However, this process can only be controlled to +/− 100 Angstroms, which can be a problem in producing Heterojunction Bipolar Transistors (HBTs), in which some layers may only be only hundreds of Angstroms thick.
Furthermore, conventional etching processes that indiscriminately etch all exposed surfaces are not well-suited to manufacture some finely detailed MEMs structures that require tighter control over subtractive processing operations.
What is needed is a process and an apparatus that facilitates selective etching to form a structure on a silicon or other substrate.
SUMMARY
One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.
In one embodiment of the present invention, the etch rate of the selective etchant through the second material is faster than the etch rate of the selective etchant through the first material and the third material, so that the second etching operation etches through the remaining portion of the second layer without significantly etching the first layer and the third layer.
In one embodiment of the present invention, receiving the silicon substrate involves, receiving the silicon substrate with the first layer composed of the first material, and applying a photoresist layer over the first layer. It also involves exposing the photoresist layer through a mask and developing the exposed photoresist layer, whereby portions of the photoresist layer defined by the mask are removed, so that portions of the first layer are exposed. Next, the process performs the first etching operation to create voids in exposed regions of the first layer, and removes the photoresist layer.
In one embodiment of the present invention, the first etching operation is a reactive ion etch.
In one embodiment of the present invention, the first material and the third material are substantially the same material.
In one embodiment of the present invention, the chemo-mechanical polishing operation takes place after forming the third layer.
In one embodiment of the present invention, the second layer is a conformal layer that fills part but not all of a void created by the first etching operation, and the third layer fills in a remaining portion of the void created by the first etching operation.
In one embodiment of the present invention, the voids created between the first layer and the third layer define one or more capillaries between the first layer and the third layer.
In one embodiment of the present invention, the first material comprises Si—Ge—C, the second material comprises Si, and the selective etchant comprises KOH. Note that the term “Si—Ge—C” is used to refer to Si
1−X−Y
Ge
X
C
Y
throughout this specification.
In one embodiment of the present invention, the first material comprises Si—Ge—C, wherein the carbon is approximately one atomic percent, the second material comprises Si, and the selective etchant is KOH—H
2
O. Note that the term KOH as used in this specification can refer to an aqueous reagent KOH diluted with H
2
O or Isopropanol or other alcohols.
In one embodiment of the present invention, the first material comprises Si, the second material comprises Si—Ge or Si—Ge—C, and the selective etchant comprises TMAH or HNA.
In one embodiment of the present invention, the second layer includes one or more silicon and/or polysilicon layers.
REFERENCES:
patent: 5906708 (1999-05-01), Robinson et al.
patent: 5914507 (1999-06-01), Polla et al.
patent: 5961877 (1999-10-01), Robinson et al.
patent: 6064081 (2000-05-01), Robinson et al.
S. Wolf, “Silicon Processing for the VLSI Era-vol. 2,” 1990, Lattice Press, vol. 2, pp. 238-239.
Hunt Charles E.
Peterson Jeffrey J.
Chaudhuri Olik
Park Vaughan & Fleming LLP
Sutton Timothy
The Regents of the University of California
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