Fabricating method of multi-level wiring structure for semicondu

Details Fabricating method of multi-level wiring structure for semicondu Fabricating method of multi-level wiring structure for semicondu

1999-05-27

2000-08-15

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438634, 438633, 438637, 438782, H01L 214763

Patent

active

06103617&

ABSTRACT:
A fabricating method of a multi-level wiring structure for a semiconductor device that improves the resolution of photoresist film pattern by reducing a photoresist film and is capable of fabricating a semiconductor device of a high reliability by using an improved via hole mask includes the steps of sequentially forming a first insulating film, a first etching stop film, a second insulating film and a second etching stop film on a lower conductive layer pattern, forming a trench by etching the second etching stop film, the second insulating film and the first etching stop film which corresponds to an upper conductive layer pattern, forming a photoresist film on an entire upper surface of the resultant semiconductor substrate so that a thin photoresist film at about 1000-3000 .ANG. is formed on the second etching stop film, forming an opening on a predetermined portion of the trench by performing a photolithography, forming a via hole by etching the first insulating film through the opening, and filling a conductive material in the via hole and the trench.

REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5677001 (1997-10-01), Wang et al.
Wolf et al., Silicon Processing , vol. 1, pp., 409-413, 430-434, 1986.

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