Fabricating method of dual damascene

Details Fabricating method of dual damascene Fabricating method of dual damascene

1998-08-20

2001-02-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S639000, C438S640000, C438S623000, C438S624000, C438S631000, C438S653000, C438S666000, C438S672000

Reexamination Certificate

active

06184126

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87109056, filed Jun. 8, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fabricating method of dual damascene, and more particularly, to a fabricating method of dual damascene that uses low-permissivity dielectric as material.
2. Description of Related Art
The cross-sectional views showing the fabrication process of a conventional fabricating method of dual damascene is shown in
FIGS. 1A through 1D
. As shown in
FIG. 1A
, in the fabrication process of a conventional fabricating method of dual damascene, a patterned conducting layer
102
is first formed on a substrate
100
, wherein the substrate
100
already contains formed devices (not shown). Then, a oxide layer
104
and a silicon nitride layer
106
are formed on the substrate
100
in sequence. Referring to
FIG. 1B
, the silicon nitride layer
106
is patterned to form an opening followed by forming an insulating layer
108
over the substrate
100
. An anisotropic dry etching process is performed to pattern the insulating layer
108
by using a photoresist layer whereon (not shown). In the meantime, a portion of the oxide layer
104
that is not covered by the patterned silicon nitride layer
106
a
is also stripped by the anisotropic dry etching process to expose the conducting layer
102
. A trench
110
b
is then formed in insulating layer
108
a
, and a hole
110
a
is formed within patterned oxide layer
104
a
and insulating layer
108
a
, as shown in FIG.
1
C. Referring to
FIG. 1D
, a barrier layer
112
is deposited on the substrate
100
first, and then, a metal layer
114
is deposited to fill the hole
110
a
and trench
110
b
. The metal layer
114
on the insulating layer
108
a
is removed by a chemical mechanical polishing process to form a via
114
a
, and conducting lines
114
b
and
114
c
in the hole
110
a
and trench
110
b.
Since the design rule of semiconductor devices gradually evolves toward the fabrication process of 0.25 &mgr;m, the widths of the via
114
a
, conducting lines
114
b
and
114
c
become accordingly narrower. The distance between conducting lines
114
b
and
114
c
is shortened as well. Therefore, the conducting lines
114
b
and
114
c
, and the insulating layer
108
a
between the conducting lines
114
b
and
114
c
behave like a capacitor which generates a undesired current, wherein the current disturbs the functions of the conducting lines
114
b
and
114
c
, and further causes RC delay that suppresses the efficiency of the device.
Moreover, in the step of forming the barrier layer
112
, a downsized opening
110
a
worsens the step coverage of the barrier layer
112
, as shown in FIG.
2
. The protuberances of the barrier layer
112
further increase the difficulty on the follow-up deposition process.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of dual damascene that forms a material of low permissivity between the conducting lines to avoid the capacitor effect caused by two conducting lines in close proximity. An enforcement process is applied on the low-permissivity material, wherein the exposed portion of the low-permissivity material is further covered by a protection layer.
In addition, a hard mask layer is formed on the low-permissivity material, wherein the hard mask layer contains openings that gradually widen upward to ensure that the openings are not choked by the subsequently deposited material. The hard mask layer can be further used as a stop for the chemical mechanical polishing process.
In accordance with the foregoing and other objectives of the present invention, the invention provides a method of dual damascene that includes forming a first conducting layer on a substrate, which already contains formed devices, forming a first dielectric layer and a hard material layer on the first conducting layer. The hard material layer contains a first opening, which is located right over the first conducting layer. A second dielectric layer is formed on the hard material layer, wherein the second dielectric layer is enforced by a ion implantation process or a plasma process. A hard mask layer containing a second opening is then formed on the second dielectric layer, wherein the second opening is gradually wider upward, and wherein the second opening is located over the first opening. The hard mask layer is then used to pattern the second dielectric layer to expose the hard material layer. A part of the first dielectric layer is removed to expose the first conducting layer and form a third opening after a protection layer is formed on the side wall of the second dielectric layer. The third opening is then filled with a barrier layer and a second conducting layer to form a via and a conducting line. The gradually widening upward second opening ensures the smoothness of the processes of depositing the barrier layer and the second conducting layer.


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