Fabricating logic and memory elements using multiple gate...

Details Fabricating logic and memory elements using multiple gate... Fabricating logic and memory elements using multiple gate...

2006-09-29

2008-09-16

Kebede, Brook (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S366000, C257S516000, C257S903000, C257SE27098, C257SE21661, C438S277000, C438S381000

Reexamination Certificate

active

07425744

ABSTRACT:
Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

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