Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-02-07
2002-09-03
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000
Reexamination Certificate
active
06444503
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to methods of fabricating electrical metal fuses.
BACKGROUND OF THE INVENTION
Current laser metal fuses require a relatively large space and are complex to fabricate when using copper (Cu) processes.
U.S. Pat. No. 6,218,279 B1 to Weber et al. describes a dual damascene copper fuse process.
U.S. Pat. No. 6,162,686 to Huang et al. describes a trench fuse process.
U.S. Pat. Nos. 5,068,706 to Sugita et al., 5,472,901 to Kapoor, 5,827,759 to Froehner and 6,100,118 to Shih et al. describe related fuse processes.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide improved methods of forming electrical metal fuses without additional masking steps.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided. A first patterned dielectric layer is formed over the substrate. The first patterned dielectric layer having at least one first opening exposing at least a portion of the substrate. A first planarized structure is, formed within the at least one first opening. A second patterned dielectric layer is formed over the first planarized structure. The second patterned dielectric layer having a second opening exposing at least a portion of the first planarized structure. A second planarized structure is formed within the second opening whereby the first planarized structure and the second planarized structure comprise the electrical metal fuse. The electrical metal fuse having a middle portion, having a thickness and a width, between two end portions each having a thickness and a width. The thickness and width of the middle portion being less than the respective thickness and width of the end portions.
REFERENCES:
patent: 5068706 (1991-11-01), Sugita et al.
patent: 5472901 (1995-12-01), Kapoor
patent: 5827759 (1998-10-01), Froehner
patent: 6100118 (2000-08-01), Shih et al.
patent: 6162686 (2000-12-01), Huang et al.
patent: 6218279 (2001-04-01), Weber et al.
patent: 6323111 (2001-11-01), Hui et al.
Ackerman Stephen B.
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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