Fabricating a top conductive layer in a semiconductor die

Details Fabricating a top conductive layer in a semiconductor die Fabricating a top conductive layer in a semiconductor die

2011-03-01

2011-03-01

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S106000, C438S109000, C438S127000, C438S637000, C438S672000, C257SE21585, C257SE21597, C257SE23067, C257SE23129, C257SE25013

Reexamination Certificate

active

07897484

ABSTRACT:
According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.

REFERENCES:
patent: 7098070 (2006-08-01), Chen et al.
patent: 7300857 (2007-11-01), Akram et al.
patent: 7427803 (2008-09-01), Chao et al.
patent: 7449784 (2008-11-01), Sherrer et al.
patent: 7704874 (2010-04-01), Kar-Roy et al.
patent: 2009/0321948 (2009-12-01), Wang et al.

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