Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-12-18
2003-07-08
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C257S351000
Reexamination Certificate
active
06589828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating thin film transistors and, more particularly, to a method for fabricating a thin film transistor having improved electrical properties.
2. Description of the Related Art
Thin film transistors are commonly used as a driving device for liquid crystal displays or as a pull-up device in a Static Random Access Memory (SRAM). Such thin film transistors are formed on an insulating substrate and have a bottom gate type structure. Thin film transistors used in the SRAM application are highly advantageous in providing improved net die yield of the semiconductor device as compared to a typical full MOS transistor.
The conventional method will be described and illustrated with reference to the fabrication of a thin film transistor suitable for use as a pull-up device in a SRAM. Various of the steps and layers are illustrated in the cross-sectional views provided in the figures.
A semiconductor substrate
1
is provided on which a predetermined lower layer
2
is formed. This lower layer
2
is preferably an insulating film that covers patterns existing on the substrate. A gate electrode
3
a
is then formed on the lower layer
2
. Reference numeral
3
b
shows a node contact line. A gate oxide film
4
is then formed on the lower layer
2
, the gate electrode
3
a
, and the node contact line
3
b
. A polysilicon film is then deposited on the gate insulating film
4
. In portions of the polysilicon layer disposed on either side of the gate electrode
3
a
, source and drain regions
5
a
,
5
b
are then formed using a conventional ion-implanting process by, for example, selectively implanting boron ions into the polysilicon film. As a result, a thin film transistor having a bottom gate type is fabricated. In this case, a portion of the polysilicon layer between the source region
5
a
and the drain region
5
b
acts as a channel region
5
c
. The source region
5
a
is partially overlapped with the gate electrode
5
c
. Also, the source/drain regions
5
a
,
5
b
are formed in such a way that a light doped offset region is formed in the drain region
5
b
in order to minimize the hot carrier effect.
However, in the prior art thin film transistor described above, the polysilicon layer acting as the channel layer is thin and thus has lower charge mobility than that provided by a typical bulk transistor. For this reason, the thin film transistor according to the prior art suffers from inferior electrical properties, such as a low on-current and a high off-current (i.e., leakage current), and thus exhibits increased signal swings.
Specifically, the polysilicon layer for the channel layer in the prior art thin film transistor has a thickness of, for example, only 200 to 300 Å. Even though the ion-implant that forms the source and drain regions utilizes a lightly doped offset (LDO) ion implantation process to minimize the hot carrier effect, the polysilicon channel layer becomes excessively doped as a result of its thinness. As a result of this excessive doping, the prior art thin film transistor exhibits degraded punch-through resistance and increased hot carrier effects.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for the fabrication of a thin film transistor having improved electrical properties.
To achieve the above object, the present invention provides a method for fabricating a thin film transistor comprising the steps of: forming a gate electrode on an insulating substrate; forming a gate oxide film on the insulating substrate and gate electrode; depositing a polysilicon layer on the gate oxide film; implanting a first impurity ion into the polysilicon layer to control a threshold voltage of the polysilicon layer; forming a first ion-implanting mask on a portion of the polysilicon layer above the gate electrode, the first ion-implanting mask having the same width as that of the gate electrode; implanting a second impurity ion into the exposed region of the polysilicon layer using the first ion-implanting mask, to form a lightly doped offset region in the drain region; removing the first ion-implanting mask; forming a second ion-implanting mask on the polysilicon layer in such a manner that the second ion-implanting mask covers a portion of the gate electrode and the lightly doped offset region; implanting a third impurity ion into the polysilicon layer using the second ion-implanting mask to form source/drain regions; and removing the second ion-implanting mask.
This and other objects and aspects of the invention will be apparent from the following description of preferred embodiments and through reference to the accompanying figures.
REFERENCES:
patent: 5910672 (1999-06-01), Iwamatsu et al.
patent: 6184070 (2001-02-01), Park
patent: 6214652 (2001-04-01), Batra et al.
patent: 6255146 (2001-07-01), Shimizu et al.
Kuroi, et al., Novel NICE (Nitrogen Implantatin into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance 0.25 um Dual Gate CMOS, IEEE, Electron Device Meeting, Dec. 1993 pp 325-328.
Coleman William David
Hyundai Electronics Industries Co,. Ltd.
Pillsbury & Winthrop LLP
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