Fabricating a substantially self-aligned MOSFET

Details Fabricating a substantially self-aligned MOSFET Fabricating a substantially self-aligned MOSFET

2001-10-25

2003-11-18

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S299000, C438S300000, C438S692000

Reexamination Certificate

active

06649460

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to MOS type semiconductor devices such as MOSFETs.
2. Description of the Related Art
A method of increasing the performance of integrated circuits is to shrink the channel length of an integrated circuit such as a MOSFET. By shrinking the MOSFET channel length, higher on-current and lower gate capacitance can be achieved, so that the overall circuit performance increases. One major challenge in shrinking the transistor channel length is to minimize well-known short channel effects. Short channel effects occur when the source and drain of the MOSFET become too close to each other, which causes the gate of the MOSFET to lose control over the channel causing uncontrollable leakage current even in the off-state of the transistor. To minimize the short channel effects, the depth of the source and drain extensions (junctions) of the MOSFET are reduced, so that the gate can have more control over the channel.
The source and drain extensions are usually formed by implanting electrically active species into a silicon layer to form n+ doped silicon for the NMOSFET source and drain extensions, and p+ doped silicon for the PMOSFET source and drain extensions. In order to reduce the depths of the source and drain extensions, the energy and dose of the implant are reduced considerably. However, even with a very low energy implant, the extension depths cannot be made very shallow because the ion implantation process will spread the dopant profile. See, for example, U.S. Pat. No. 5,903,027, MOSFET with Solid Phase Diffusion Source, issued May 11, 1999, by Toshitomi, et al., and “Sub-50 NM Gate Length N-MOSFETS with 10 NM. “Phosphorous Source and Drain Junctions,” by Ono, et al.,
IEDM
93 which are hereby incorporated by reference in their entireties. In addition, substantial alignment (substantial coplanarity) of certain vertical surfaces of the gate with certain proximate vertical surfaces of the source and drain extensions helps reduce not only short channel effect but also stray capacitance problems. Various substantially self-aligned MOSFETs and fabrication methods are known.
However, the present inventors believe that known methods for creating substantially (ie, within 10% tolerance) self-aligned MOS type semiconductor devices have not proven to be entirely satisfactory.
SUMMARY OF THE INVENTION
The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (such as a first polysilicon) having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material (such as a second polysilicon) in the trench and over the vertical and horizontal surfaces, the second material having a substantially (eg, ±10%) uniform thickness so as to form a notch over the trench; providing a masking material (such as an oxide or a nitride) into the notch, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.
The inventive process results in at least a substantially self-aligned gate and uses, eg, known CMP (chemical mechanical polishing/planarization) method that is easy to implement.
Also, CMP to planarize the polysilicon extensions is also easy to implement.
It is an object of the present invention to provide a novel method for fabricating an at least substantially self-aligned semiconductor device.
It is an additional object of the present invention to provide a novel structure useful for fabricating an at least substantially self-aligned semiconductor device such as a MOSFET.
Further and still other objects of the present invention will become more readily apparent when the following detailed description is taken in conjunction with the following drawing figures.


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