Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-18
2002-07-30
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000, C257S328000, C257S329000, C257S330000, C257S331000, C257S332000, C438S303000, C438S305000
Reexamination Certificate
active
06426524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a square spacer and an associated method of fabrication.
2. Related Art
Sidewall features known as “spacers” are used in electronic packages and are formed in abutment with such electronic features as gates, conductive lines, transistors, and inherent topography. Such a feature is characterized by a vertical wall against which a spacer can be formed. In particular, a stack of spacers are commonly formed as arrayed in a horizontal direction with a first spacer of the stack abutting the vertical wall of the feature. Each spacer in the stack is parallel to the vertical wall and more distant from the vertical wall than the immediately preceding spacer. An array of 1 to 3 spacers in such a stack is common. With current methods of spacer formation, a spacer formed in abutment with a wall does not have a horizontal top surface but rather has a top surface with a rounded corner on that portion of the top surface that is most distant from the wall. The rounded corner results from a plasma etching process that utilizes isotropic distributions of particles, such as ionized plasma particles, for etching a material from which the spacer is formed, as well as from the topography of the material to be etched. Unfortunately, the rounded corner of a given spacer reduces the vertical height of the side of the spacer that includes the rounded corner. As a result, less vertical height is available for the next spacer in the stack in the horizontal direction away from the feature; i.e., the height of successive spacers in the stack are reduced. For example, if the first spacer (i.e., the spacer abutting the feature) in the stack is 2000 Å high, then the second and third spacers in the stack may be limited to vertical heights of only 1400 Å and 1000 Å, respectively. Even worse, the width of successive spacers in the stack are also reduced because fabrication methods generally limit a spacer width to be no greater than about two-thirds of the spacer height. Thus, current fabrication methods limit both successive vertical heights and the total cumulative width of a stack of spacers that abut a feature of the electronic package. A particular disadvantage associated with the limitation on successive vertical height is that insulative spacers between conductive structure on the electronic package may have insufficient height or width to prevent undesired diffusion of conductive material from one conductive structure to another, resulting in shorting over the spacer.
A method is needed for fabricating a square spacer having a flat horizontal top surface.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a square spacer, comprising the steps of:
providing a mandrel;
forming a first layer over two intersecting sides of the mandrel, said first layer including a first material;
forming a second layer over the first layer, said second layer including a second material; and
forming the square spacer by:
etching away a portion of the first layer; and
etching away a portion of the second layer.
The present invention provides an electronic structure comprising a square spacer, said square spacer having:
a mandrel on a surface of a substrate;
a first region of a spacer material abutting the mandrel and on the surface of the substrate;
a second region of the spacer material abutting a portion of the first region and on the substrate; and
a region of oxide material abutting a remaining portion of the first region and on the second region, wherein a height of the oxide region above the surface of the substrate is about equal to a height of the first region above the surface of the substrate.
The present invention has the advantage of providing a square spacer with a horizontal top surface that enables a stack of spacers to have substantially greater successive vertical heights and a total cumulative width for a stack of spacers than is the case with a conventional stack of spacers having rounded corners.
The present invention has the advantage of being able to form a stack of insulative spacers that is high and wide enough to prevent undesired diffusion of conductive material from a conductive structure on one side of the stack to another conductive structure on the opposite side of the stack.
The horizontal top surface of a spacer of the present invention has the advantage of making it easier to lithographically align a second mask over a first mask than with a rounded surface, because a rounded surface has less visual contrast with surrounding features, and requires a larger focal window, than does a square surface; i.e., it is easier to recognize where an end of a spacer is if the spacer has a sharply defined square corner rather than a rounded surface.
The horizontal top surface of a conductive spacer of the present invention has the advantage of making it easier to form an electrical contact on top of a conductive spacer than with a rounded surface, because a contact can land only on a flat surface and not on a sloped surface.
The horizontal top surface of a square polysilicon spacer of the present invention has the advantage of allowing formation of a silicide over the square polysilicon spacer.
REFERENCES:
patent: 5250836 (1993-10-01), Miura et al.
patent: 5281557 (1994-01-01), Yu
patent: 5372960 (1994-12-01), Davies et al.
patent: 5411906 (1995-05-01), Johnson et al.
patent: 5541427 (1996-07-01), Chappell et al.
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5776660 (1998-07-01), Hakey et al.
patent: 5789920 (1998-08-01), Andricacos et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5863824 (1999-01-01), Gardner et al.
patent: 5879985 (1999-03-01), Gambino et al.
patent: 5907775 (1999-05-01), Tseng
patent: 5966600 (1999-10-01), Hong
patent: 6040210 (2000-03-01), Burns et al.
patent: 6077745 (2000-06-01), Burns et al.
patent: 6093614 (2000-07-01), Gruening et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6118135 (2000-09-01), Gonzalez et al.
patent: 6225176 (2001-05-01), Yu
patent: 6242317 (2001-06-01), Gardner et al.
patent: 6271096 (2001-08-01), Jan et al.
Johnson Arthur Paul
Lam Chung Hon
Rankin Jed Hickory
Willets Christa Regina
Everhart Caridad
Sabo William D.
Schmeiser Olsen & Watts
Yevsikov V.
LandOfFree
Fabricating a square spacer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabricating a square spacer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabricating a square spacer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2822429