Fabricated layered capacitor for a digital-to-analog converter

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S296000, C257S298000, C257S306000, C257S307000, C257S308000, C341S150000

Reexamination Certificate

active

07446365

ABSTRACT:
A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

REFERENCES:
patent: 6690570 (2004-02-01), Hajimiri
patent: 6743671 (2004-06-01), Hu et al.
patent: 2006/0261394 (2006-11-01), Chien

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