F-SRAM power-off operation

Details F-SRAM power-off operation F-SRAM power-off operation

2011-03-01

2011-03-01

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S117000, C365S149000, C365S189040

Reexamination Certificate

active

07898837

ABSTRACT:
A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.

REFERENCES:
patent: 6809949 (2004-10-01), Ho
patent: 7149137 (2006-12-01), Rodriguez et al.
patent: 7212427 (2007-05-01), Ho
Masui et al., “A Ferroelectric Memory-Based Secure Dynamically Programmable Gate Array,” IEEE J. Solid-State Circuits; vol. 38; p. 715; May 2003.

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