F-SRAM margin screen

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S149000, C365S201000, C365S226000

Reexamination Certificate

active

07889535

ABSTRACT:
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

REFERENCES:
patent: 6836425 (2004-12-01), Kang et al.
patent: 2010/0296329 (2010-11-01), Summerfelt et al.
Shoichi Masui et al., “A Ferroelectric Memory-Based Secure Dynamically Programmable Gate Array,” IEEE Journal of Solid-State Circuits; pp. 715-725; vol. 38, No. 5; May 2003. Fujitsu Laboratories, Ltd.; Akiruno, Japan.
Tohru Miwa et al., “NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors,” IEEE Journal of Solid-State Circuits; pp. 522-527; vol. 36, No. 3; Mar. 2001. System Devices and Fundamental Research, NEC Corporation; Kanagawa, Japan.
Tohru Miwa et al., “A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM,” Symposium on VLSI Circuits Digest of Technical Papers; pp. 129-132; 2001. Silicon Systems Research Laboratories, NEC Corporation. ULSI Device Development Division, NEC Corporation; Kanagawa, Japan.

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