Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-07-16
2004-09-21
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S745000, C438S754000, C216S105000
Reexamination Certificate
active
06794292
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an improved wet cleaning approach to backend of line (BEOL) processes. More particularly, the present invention relates to an improved two-step wet cleaning process incorporated with an extrusion inhibition step for post-etch copper structures, particularly, for copper-dual damascene structures. The two-step wet cleaning process comprises a mild oxidation step followed by an oxide etch step. This approach demonstrates clean copper dual damascene structures having no copper extrusions that arise due to oxidation-reduction (“redox”) reactions in a wet cleaning solution abundant in dissolved copper ions.
2. Description of the Prior Art
Aluminum alloys with SiO
2
dielectrics have been the materials of choice for interconnect systems since the dawn of the integrated circuit (IC) era. These materials were convenient to process using mature subtractive etch processes for metal line patterning. However, as ICs have relentlessly marched down the path towards smaller geometry in the pursuit of increased speed and integration density, the traditional Al/SiO
2
interconnect system has shown itself to be a limiting factor. Cu-dual damascene architectures with low-k dielectrics are thus developing and becoming the norm now in forming interconnects in the BEOL processes.
Although Cu/low-k materials present many benefits from a circuit perspective, they require an entirely new process technology for interconnect fabrication.
Fortunately, many of these process issues have been addressed with intermediate interconnect systems employing Cu metal with low-k dielectrics. Some of these low-k materials include FLARE™, SiLK™ and BCB (porous dielectrics). This Cu/low-k material process flow led to the development of Cu dual damascene processes in order to overcome the difficulties presented with reactive ion etching (RIE) of Cu. However, processing with these Cu/low-k material systems presents an entirely new set of problems that must be overcome. Etching vias and trenches results in the formation of complex organometallic polymers, which are difficult to clean using dry processes. Since Cu does not possess the self-passivating properties of Al, the tendency of Cu to corrode when exposed to an oxidizing environment is also a major concern. This is especially problematic with the wet immersion processes required for cleaning Cu/low-k etch residues.
One approach typically used to clean copper structures after via/trench dry etch is using a very diluted aqueous HF-based cleaning process. An alternative approach featuring its effectiveness, which was developed by Mattson Technology Wet Process Division (Exton, Pa.) and United Microelectronics Corp. (Hsinchu, Taiwan), includes a two-step process based on the diluted HF-based cleaning process. The first step of the two-step process is a mild oxidation step consisting of a dilute H
2
O
2
solution 36:1 and a surfactant with megasonics irradiation. This step removes some polymer residues and the sputtered Cu on the sidewalls of the vias and trenches, and oxidizes the copper surface. The first step can be used without a surfactant. The second step is a mild oxide etch utilizing dilute HF, NH
4
F or NH
2
OH. This step undercuts the polymer residues and removes both leftover sputtered copper from the sidewalls, and oxide, such as CuO
x
and Cu(OH)
2
, from the copper surface.
Referring now to
FIG. 1
of a post-etch dual damascene structure
30
formed on a silicon substrate
10
, in an acidic ambient, such as HF solution, the lift CuO
x
and Cu(OH)
2
molecules dissolve and thus produce massive copper ions (Cu
2+
) in the solution (see eq. 1). In
FIG. 1
, after dipping the silicon substrate
10
into an acidic oxide etch solution for a certain time period, a recess
13
formed due to the Cu loss is observed at a top surface of a metal-1 (M-1), i.e. first level metal, Cu wiring line
22
which is electrically connected with a P
+
diffusion region
12
of the silicon substrate
10
via a tungsten plug
16
. In the meantime, an undesirable extrusion
15
is formed atop an adjacent M-1 Cu wiring line
24
which is electrically connected with a N
+
diffusion (electron-rich) region
12
of the silicon substrate
10
via a tungsten plug
18
. A reasonable explanation for this phenomenon is that the P-N junction fabricated in the silicon substrate
10
provides an electrical path for electrochemical reactions. Excessive copper ions deposit on the anode (i.e. N
+
region connected Cu wiring line) due to reduction reaction (see eq.2). In the reduction of cupric oxide the oxidation number of copper has changed from +2 to zero by the gain of two electrons.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide an improved post-etch dual damascene wet cleaning process to alleviate the above-mentioned extrusion problems.
According to the preferred embodiment, the present invention provides an extrusion-free wet cleaning process for post-etch Cu-dual damascene structures. The process comprises the following steps:
(1). providing a wafer comprising a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N
+
diffusion region of the silicon substrate, and a trench structure formed on the via structure;
(2). applying a diluted H
2
O
2
solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line;
(3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH
4
F or NH
2
OH; and
(4). providing means for preventing Cu reduction reactions on the Cu wiring line.
According to one aspect of the present invention, the method of preventing Cu reduction reactions on the Cu wiring line is purging the wafer with inert gas during the wash of wafer by the diluted H
2
O
2
solution.
According to another aspect of the present invention, the method of preventing Cu reduction reactions on the Cu wiring line is adding a Cu corrosion inhibitor such as benzotriazole (BTA) into the diluted H
2
O
2
solution.
According to another aspect of the present invention, the method of preventing Cu reduction reactions on the Cu wiring line is reducing the H
2
O
2
concentration of the diluted H
2
O
2
solution to below 100:1 (v/v).
According to another aspect of the present invention, the method of preventing Cu reduction reactions on the Cu wiring line is lowering the temperature of the diluted H
2
O
2
solution during the wash of the wafer to below 15° C.
According to another aspect of the present invention, the method of preventing Cu reduction reactions on the Cu wiring line is increasing the pH of the acidic cupric oxide cleaning solution to above 7.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 3773577 (1973-11-01), Shibasaki et al.
patent: 6037258 (2000-03-01), Liu et al.
patent: 6054061 (2000-04-01), Bayes et al.
Hsu Winston
Umez-Eronini Lynette T.
United Microelectronics Corp.
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