Extremely low current load device for integrated circuit

Details Extremely low current load device for integrated circuit Extremely low current load device for integrated circuit

1978-11-03

1981-02-17

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

307238, 357 45, G11C 1140

Patent

active

042518768

ABSTRACT:
A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

REFERENCES:
patent: 3560764 (1971-02-01), McDowell
patent: 3986173 (1976-10-01), Baitinaer et al.
patent: 4001762 (1977-01-01), Aoki et al.

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