Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-11
2001-08-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06272671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains generally to electrical computers and more particularly to program products and methods for extracting and graphically or textually representing electronic circuit components and connections.
2. Description of Related Art
Modern electronic chip designers commonly employ circuit design representations to design and simulate electronic circuits. A traditional method of generating such design representations required circuit designers to connect logic symbols representing logic cell instances to specify a circuit design. Typically, a designer selected and placed the logic cell instances in a virtual design representation on a computer screen. The designer could then indicate connections between various logic cells by “drawing” lines connecting such logic symbols on the computer screen. The graphical representation of the design is referred to as a “circuit schematic”. Furthermore, a non-graphical design representation may be generated from the schematic, including textual netlists and binary design databases. A netlist is typically a list of electronic logic cells with a description of the interconnections between the inputs and the outputs of the various logic cells instances. A popular netlist format is Electronic Design Interchange Format (EDIF), described in “Designer's Guide to EDIF”, E. Marx et al., EDN 1987, and specified in “EDIF Electronic Design Interchange Format Version 200”, ANSI/EIA Standard 548, specifically incorporated herein by reference for all that they teach and disclose. Generally, EDIF is a standardized netlist format, which has a LISP-like syntax and is intended to simplify data transfer between CAD/CAE systems.
A microelectronic circuit designer typically combines logic cells from a logic cell library to achieve the desired functionality in a circuit. A logic “cell” in the logic cell library can be defined by an EDIF netlist containing a cell model that specifies structural, functional and timing information. The cell model is typically defined, at least in part, by one or more “primitives”. A primitive is a standard logic model, defined by a simulator vendor, that describes a fundamental logic block understood by a simulator (e.g., NAN2, AND2, etc.). A cell model designer uses primitives to develop a set of standard library cells for use by circuit designers. For example, a cell model designer might define an AND4 (i.e., a four input AND gate) library cell to comprise three AND2 (i.e., a two input AND gate) primitives. When a circuit design containing the AND4 cell is instantiated in a design and simulated, the simulator understands the operation of the AND4 based on its three AND2 primitives.
When a library cell is included (or instantiated) in a design, a “cell instance” is created in the design, which may also be defined by an EDIF netlist. A “design” refers to the hierarchical levels in a circuit design and typically includes a combination of component “cell instances” and/or “primitive instances”. Each component cell instance may also include a combination of other cell instances and primitive instances. A single cell may be instantiated in a design multiple times, and each cell instance is typically given a unique identifier. Because an EDIF netlist may be hierarchical (i.e., represent many layers of circuitry), the unique identifier for the cell instance often includes a path name for defining the cell instance within the design hierarchy.
The circuit design terms used above may be analogized to a computer directory structure. The root computer directory is analogous to the “top” level of a circuit design hierarchy. In addition, a computer directory structure can have multiple layers of sub-directories within sub-directories. Likewise, an EDIF netlist for a design can have cell instances within cell instances (i.e., the design hierarchy). An individual sub-directory is typically defined by a unique directory path name; an individual cell instance is defined by a unique instance path name. A sub-directory may possess both files that terminate the directory path or subdirectories; a cell instance may possess both primitives that terminate the design hierarchy path or other cell instances.
Generally, the hierarchical nature of the EDIF format, its LISP-like syntax, and the inherent complexity of many circuit designs combine to form an EDIF netlist that is very complicated and difficult for a human to read, unless the user is very familiar with the design or experienced with the EDIF format. Accordingly, a need exists to simplify or translate the EDIF design representation to allow an EDIF-novice or a designer who is unfamiliar with a particular design to quickly understand the design, without requiring a detailed analysis of the EDIF netlist itself.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a simplified representation of a design using translation of a netlist or other design representation.
It is another object of the present invention to extract specific instance and connectivity information from a design representation and to graphically or textually represent it in user-readable format.
It is yet another object of the present invention to generate a graphical schematic of a circuit by extracting cell instances, primary ports, component instances, component ports, and signal information from a netlist or other design representation.
It is yet another object of the present invention to generate an EDIF netlist of a library cell from a simplified data file.
Additional objects, advantages, and novel features of the invention are set forth in the description that follows and will become more apparent to those skilled in the art when taken in conjunction with the accompanying drawings. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and accommodations particularly pointed out in the appended claims.
To achieve the foregoing and other objects, in accordance with the purposes of the present invention, as embodied and broadly described herein, the program storage medium of this invention may comprise instructions for locating the circuit in said design representation; extracting from the design representation a predetermined subset of data defining the circuit; formatting the predetermined subset of circuit data into a user-readable format including at least one element having a component instance name, a component celltype, a component port name, and a signal name; and outputting the predetermined subset of circuit data in the user-readable format.
The present invention may also comprise, in accordance with its object and purposes, a method having the steps of locating the circuit in the design representation; extracting from the design representation a predetermined subset of data defining the circuit; formatting the predetermined subset of circuit data into a user-readable format including at least one element having a component instance name, a component celltype, a component port name, and a signal name; and outputting the predetermined subset of circuit data in the user-readable format.
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LSI Logic Corporation
Siek Vuthe
Smith Matthew
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