Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-07-30
2008-03-25
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000, C703S016000
Reexamination Certificate
active
07350167
ABSTRACT:
A method for extracting capacitance from a layout record includes solving a matrix equation to obtain a set of capacitors that account for metal fill while eliminating floaters. A method for extracting capacitance from a layout record includes partitioning floaters into disjoint sets, and converting a capacitance matrix into block-diagonal form by ordering conductors according to the disjoint sets.
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Bingham & McCutchen LLP
Cadence Design Systems Inc.
Kik Phallaka
LandOfFree
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