Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-28
2004-07-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06766498
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of electronic design automation, and more particularly to extracting the parasitic resistances and capacitances of selected interconnections in an integrated circuit using less memory and processing power than in prior art.
BACKGROUND INFORMATION
A field, commonly referred to as “Electronic Design Automation (EDA)”, has evolved to handle the demanding and complicated task of designing semiconductor integrated circuits. EDA may refer to using a computer to design and simulate the performance of electronic circuits on an integrated circuit, commonly referred to as a “chip”. Computers may be ideally suited to perform tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of simpler functions.
After the circuit for a semiconductor chip has been designed and physically laid out, the operation of the integrated circuit may be tested to verify the chip is working properly. One of the tests may be to characterize the parasitic effects associated with the interconnections, i.e., the wiring or nets, between electronic devices, e.g., transistors, in the chip. That is, one of the tests may be to characterize the wiring resistance and capacitance parasitics referred to herein as “Resistance Capacitance (RC) extraction”. These wiring parasitic effects arise from the semiconductor manufacturing process. Wiring parasitics are important to characterize because they impact the delay of electronic signals from one point to another point in the chip and hence may impact the processing speed. Signals may take a longer time to propagate from one point to another point in the chip by the resistances and/or capacitances imposed upon the signal path. Further, parasitic effects may impact what is commonly referred to as “electromigration.” Electromigration may refer to the problem of having the metal in the signal lines migrate along the path of the current flow over time. Eventually over a period of time, e.g., several years, this electromigration may result in an open circuit so that the signal is interrupted in the signal path thereby causing the chip to fail. High current density which may cause electromigration may result from a large capacitance load.
One method for characterizing the parasitic resistances and capacitances of the interconnections may be to assume that the parasitic resistance and capacitance for each metal layer in the interconnections to be a constant value per unit length. However, the actual parasitic effects in the lengths of interconnections are not constant per unit length but vary with metal line width, dielectric thickness and other fabrication and design characteristics. Therefore, the method may produce inaccurate results especially for interconnections comprising multiple complex interconnect layers.
More accurate methods for performing RC extraction have been developed by EDA vendors. For example, one software tool, commonly referred to as STAR-R software from AVANT! CORPORATION, performs RC extraction to calculate delay of electronic signals using a 4-step extraction process. First, a capacitance-only (C-only) extraction is performed on every interconnection in the design. Second, only resistance is extracted on every interconnection in the design (R-only). Third, delay calculations are performed to compare the R-only delay to the C-only delay. The delay calculations consume a significant amount of CPU time. On an interconnection by interconnection basis, if the difference between the R-only delay and the C-only delay exceeds a certain error criteria, the interconnection is identified for detailed parasitic RC extraction. Fourth, detailed extraction is performed on the identified interconnections using a distributed impedance model to address the complexity of the narrow metal spacing and other deep submicron effects. While EDA vendors may have developed tools that more accurately performs RC extractions, these tools require compute-intensive RC extractions for each interconnection thereby requiring a significant amount of memory and processing power.
It would therefore be desirable to develop a tool that accurately simulates performance of the integrated circuit yet avoids compute-intensive RC extractions for each interconnection by performing RC extractions on selected interconnections in an integrated circuit thereby using less memory and processing power than in prior art.
SUMMARY
The problems outlined above may at least in part be solved in some embodiments by identifying a selected number of interconnections in the integrated circuit (“interconnections of interest”) and pruning a netlist containing a list of the transistors in the integrated circuit by selecting only those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may then be associated with the transistors connected to those layout layers in the pruned netlist. By using a pruned netlist of transistors in channel connected regions on the driving side of the interconnections of interest and transistors on the receiving side of the interconnections of interest, less compute-intensive RC extractions may be made thereby using less memory and processing power than in prior art. Furthermore, by associating the parasitic capacitance and resistance values of each of the extracted layout layers to each of the transistors in the pruned netlist, an accurate simulation of the performance of the integrated circuit may be made.
In one embodiment of the present invention, a method for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit may comprise the step of identifying a particular interconnection (“interconnection of interest”). Transistor(s) in channel connected region(s) on the driving side of the interconnection of interest and transistor(s) on the receiving side of the interconnection of interest may then be identified. That is, transistor(s) in channel connected regions(s) that are connected to the driving side of the interconnection of interest and transistor(s) connected to the receiving side of the interconnection of interest may be identified.
The layout layers connected to the interconnection of interest may then be extracted from the overall layout of the integrated circuit. That is, anything electrically connected to the interconnection of interests may be extracted. The parasitic capacitance and resistance values for each of the extracted layout layers may be extracted. The extracted parasitic capacitance and resistance values for each of the extracted layout layers may be associated with the identified transistor(s) on the driving side and on the receiving side of the identified interconnection of interest.
The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
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Bell Joshua A.
Newmark David M.
Sharma Mahesh S.
Singh Teja
Advanced Micro Devices , Inc.
Siek Vuthe
Voigt, Jr. Robert A.
Winstead Sechrest & Minick P.C.
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