Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-01-08
1999-11-02
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711100, 711 1, 711101, 714805, G06F 1214
Patent
active
059788909
ABSTRACT:
In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending data according to the command-chaining time between main and sub disk control devices. A section for judging cable length and function of the sub disk control device 36 estimates command-chaining time between a pair of main and sub disk storage devices. The channel command analyzing section 31 estimates the number of records to be transferred and the length of a record using a LOCATE RECORD command. The command judgment section for the sub disk control device 32 optimizes the command-chain to be issued to the sub disk control device using the above-mentioned information. Then, the section for issuing command to the sub disk control device 35 issues the optimized command chain. Thus, a shorter transmission time is realized by either sending individual records or an entire track of data.
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Koide Takeshi
Nakamura Katsunori
Ozawa Koji
Sano Kazuhide
Cabeca John W.
Hitachi , Ltd.
Tzeng Fred F.
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