Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2005-08-23
2005-08-23
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C711S118000, C711S154000, C711S118000, C711S205000
Reexamination Certificate
active
06934780
ABSTRACT:
An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.
REFERENCES:
patent: 4112489 (1978-09-01), Wood
patent: 5255211 (1993-10-01), Redmond
patent: 5619723 (1997-04-01), Jones et al.
patent: 6665755 (2003-12-01), Modelski et al.
“An efficient high-speed block turbo code decoding algorithm and hardware architecture design” by Kyungchul Yoo, Hyungshik Shin, Yunho Jung, Junghyuck Lee, Jaeseok Kim (abstract only).
“Few decoders in the encoder: a low complexity encoding strategy for H.26L” by Olmo, G.; Cucco, C.; Grangetto, M.; Magli, E. (abstract only).
Craren Michael J.
Kristiansen Adrian M.
Modelski Richard P.
Nortel Networks Limited
Ray Gopal C.
Steubing McGuinness & Manaras LLP
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