Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-19
1999-05-04
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518305, 39518314, 39518315, 395704, 395568, G06F 1208, G06F 1130
Patent
active
059000147
ABSTRACT:
A system for facilitating debugging of software running within an information processing unit includes an external trigger state machine which selectively overrides the cacheability attribute of a cache line. An in-circuit emulator (ICE), which is used for debugging purposes, monitors addresses read by and written to a CPU. If an address which is of interest for debugging purposes is detected by the ICE, then the ICE issues a trigger signal. The trigger signal causes the external trigger state machine to designate the cache line associated with the detected address as a non-cacheable operation (i.e., to override the cacheability attribute) . Thus, the data associated with the cache line is written out to the main memory module where the data can be observed by an ICE, rather than to an internal cache memory location where the data would be invisible to an ICE. In a preferred embodiment of the invention, the external trigger state machine is configured to operate in a pipelining environment wherein multiple requests may be outstanding at one time.
REFERENCES:
patent: 4758946 (1988-07-01), Shar et al.
patent: 4885680 (1989-12-01), Anthony et al.
patent: 5075846 (1991-12-01), Reininger et al.
patent: 5249281 (1993-09-01), Fuccio et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5327545 (1994-07-01), Begun et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5404464 (1995-04-01), Bennett
patent: 5463760 (1995-10-01), Hamauchi
patent: 5619677 (1997-04-01), Nishimukai et al.
patent: 5636363 (1997-06-01), Bourekas et al.
Atmel Travels New Worlds, Electronic Buyers' News Mar. 14, 1994, p.14.
Case Brian, ARM600 targets low-power applications: ARM core extended with 32-bit addressing, "object oriented" MMU, Microprocessor Report, v5, n23, p8(4), Dec. 18, 1991.
Gallant, Protocols keep data consistent; cache-coherency protocols, EDN, v36, n6, p41(6), Mar. 14, 1991.
Shear, David; Teaming a Logic Analyzer with a Debugger Provides Advantages to Both Tools, EDN-Technology Update, Jan. 20, 1994 pp. 21-26.
AST Research Inc.
Bragdon Reginald G.
Chan Eddie P.
LandOfFree
External means of overriding and controlling cacheability attrib does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with External means of overriding and controlling cacheability attrib, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and External means of overriding and controlling cacheability attrib will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1867350