Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-06-10
2000-01-04
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711111, 711112, 711113, 711154, 371 492, 371 511, G06F 1208, G06F 1320, G06F 1110
Patent
active
060121238
ABSTRACT:
An external I/O controller system between a host system and a Redundant Array of Independent Disks (RAID) array, having a processor complex for coordinating RAID parity write operations to a member disk in a RAID array, and a cache memory complex that asynchronously executes the RAID parity write operation independent of the processor complex and any processor complex resources. The cache memory complex includes a first cache memory and a second cache memory that operate in concert to achieve increased RAID parity write efficiency for a RAID Level 3, 4, 5, or 6 write operation. The I/O controller of the present invention also performs substantially concurrent manipulations on the new host data being written to the RAID array and the old host data and old parity data used to generate a new parity data corresponding to the new host data.
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Davies Ian R.
Pecone Victor Key
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