External contact to a MOSFET drain for testing of stacked-capaci

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257296, 257301, 257303, 257 68, 257 71, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

059145129

ABSTRACT:
A structure for forming an ohmic contact to the drain of a MOSFET in a stacked capacitor DRAM cell is described. The contact is formed by making an opening in the upper cell plate of the cells capacitor and contacting the storage plate through this opening with a conductive plug, preferably a tungsten plug. The plug is formed concurrent with the conventional contact and first metal wiring processing of the DRAM. The contact is used in DRAM test arrays for characterizing the quality of MOSFET gate insulator as well as the performance characteristics of the MOSFET itself. Connection to the conductive plug is made with first metal wiring. The test structures can be built at any position within the array and since they are located above the polysilicon bitline/wordline structure, the metal connection lines for the contacts do not interfere with the structure of the test array itself other than the sacrifice of the test cell from the array. Multiple devices may be designated from anywhere in the array, and probe contacts may be conveniently located on the chip.

REFERENCES:
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5235549 (1993-08-01), Young et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5808855 (1998-09-01), Chan et al.

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