Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1998-06-30
2001-01-09
Yoo, Do Hyun (Department: 2751)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S105000, C714S710000
Reexamination Certificate
active
06173357
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for accessing synchronous dynamic random access memories. More specifically, the invention relates to an apparatus for combining partially defected synchronous dynamic random access memories.
BACKGROUND OF THE INVENTION
In the electric industry, memory devices are of vital applications in various kinds of system like computers and other peripherals. With the increasing demand on system operating speed and performance, more and more high speed and reliable memory devices are employed. DRAM (dynamic random access memory) is one of the most important devices in the semiconductor devices. In last decade, DRAM cells and chips are widely applied in computer systems for it's fast and reliable characteristics.
In the semiconductor manufacturing process of making memory chips, numerous processes are performed to make a great number of memory chips on a single wafer. Some defects may be found under the complex manufacturing steps and densely packed circuits. The undesired defects cause some of the memory chips to be defective ones and thus influence the yield of the products. However, most of the defective chips are only partially defected and a lot of workable cells are still left on the chips. By the design and the addition of external compensating circuits, two or more memory chips can be combined as a workable, defect-free one. Most of the partially defective chips can be merged to produce workable memory chips with undamaged functionality. Thus the cost can be reduced and the yield can be increased by reworking the defective chips to a workable one.
In system applications, DRAM can be classified into several types, like fast page mode DRAM, EDO (extended data output) DRAM, and SDRAM (synchronous DRAM). Various compensating method can be employed for combining defective fast page mode DRAM or EDO DRAM chips. In the U.S. Pat. No. 5,640,353 to the applicant of the present invention, an external compensation apparatus and method for fail bit DRAM is disclosed. The method is implemented by transforming and controlling address bits to replace defective bits. Referring to
FIG. 1
, the compensation apparatus has a tag address region
304
, a compensation data region
305
, a control logic
306
, and a comparator
300
. Thus bit defects of DRAM devices can be compensated to ensure the functionality of the system.
However, the address bit transforming and controlling scheme of the prior art method can not be applied on SDRAMs. In general, the operating mode of SDRAM cells are programmed by internal registers. The system has to program the registers of SDRAM cells by an address bus before operation. If the prior art external compensating scheme is used, a portion of the address of the SDRAM is fixed at a constant high or a constant low state. Some of the address are occupied and can not be used to program the internal registers. Thus the combined SDRAMs can not be operated by the conventional compensation scheme.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected synchronous dynamic random access memories can be combined as a workable device for being programmed and operated in the same way as a defect-free chip.
An apparatus for combining partially defected synchronous dynamic random access memory chips of the present invention includes a workable block selecting circuit and a chip selecting circuit. The workable block selecting circuit is responsive to a reference signal for selecting workable blocks of the synchronous dynamic random access memories. The chip selecting circuit is responsive to a chip selecting signal and the reference signal for selecting a chip from the synchronous dynamic random access memory chips.
Nine embodiments corresponding to different defect modes of the memory chips are disclosed in the present invention. Corresponding to different defects modes, the reference signal can be a bank selecting signal, an address reference signal of row addresses, or an address reference signal of column addresses.
REFERENCES:
patent: 4366535 (1982-12-01), Cedolin et al.
patent: 5452258 (1995-09-01), Hotta
patent: 5537665 (1996-07-01), Patel et al.
patent: 5640353 (1997-06-01), Ju
patent: 5684973 (1997-11-01), Sullivan et al.
patent: 5701270 (1997-12-01), Rao
patent: 5764575 (1998-06-01), Kawai et al.
patent: 5793942 (1998-08-01), Shoji
patent: 5841957 (1998-11-01), Ju et al.
patent: 5943693 (1999-08-01), Barth
Nath & Associates
Novick Harold L.
Shinemore Technology Corp.
Verbrugge Kevin
Yoo Do Hyun
LandOfFree
External apparatus for combining partially defected... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with External apparatus for combining partially defected..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and External apparatus for combining partially defected... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2480273